From eec8972a5bc744eda695a86a984d746c240dff90 Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Thu, 6 Dec 2012 20:30:35 +0100 Subject: target-mips: Fix incorrect reads and writes to DSPControl register Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used in the MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32 these bits must be written as zero, and return zero on read. The change fixes writes (WRDSP) and reads (RDDSP) to the register. It also fixes the tests that use these instructions, and makes them smaller and simpler. Signed-off-by: Petar Jovanovic Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'target-mips') diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 14daf91950..acf7ceb1d1 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3948,7 +3948,11 @@ void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env) if (mask[4] == 1) { overwrite &= 0x00FFFFFF; newbits &= 0x00FFFFFF; +#if defined(TARGET_MIPS64) newbits |= 0xFF000000 & rs; +#else + newbits |= 0x0F000000 & rs; +#endif } if (mask[5] == 1) { @@ -3999,7 +4003,11 @@ target_ulong helper_rddsp(target_ulong masknum, CPUMIPSState *env) } if (mask[4] == 1) { +#if defined(TARGET_MIPS64) temp |= dsp & 0xFF000000; +#else + temp |= dsp & 0x0F000000; +#endif } if (mask[5] == 1) { -- cgit v1.2.3