From a9a95061715ca09abff56a3f239f704c410912c2 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Tue, 15 Mar 2016 09:59:36 +0000 Subject: target-mips: enable CM GCR in MIPS64R6-generic CPU Indicate that in the MIPS64R6-generic CPU the memory-mapped Global Configuration Register Space is implemented. Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target-mips') diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 3192db0960..b44df9e5da 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -663,7 +663,8 @@ static const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | -- cgit v1.2.3