From ebabb67a17b58c729e12523cb21b2d6c1d93abc6 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Tue, 26 Apr 2011 10:29:36 +0200 Subject: Fix typo in code and comments Replace writeable -> writable Signed-off-by: Stefan Weil Signed-off-by: Stefan Hajnoczi --- target-mips/translate_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target-mips') diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 590e092a1d..8d9b5b9c49 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -477,7 +477,7 @@ static const mips_def_t mips_defs[] = .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), .SYNCI_Step = 16, .CCRes = 2, - .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writeable*/ + .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), .SEGBITS = 40, .PABITS = 40, -- cgit v1.2.3 From ff2712ba8938afe204dcbb0b50036b36fe057c42 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Thu, 28 Apr 2011 17:20:35 +0200 Subject: Fix typos in comments (interupt -> interrupt) Signed-off-by: Stefan Weil Signed-off-by: Stefan Hajnoczi --- target-mips/translate_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target-mips') diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 8d9b5b9c49..d55c522bf3 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -38,7 +38,7 @@ ((1 << CP0C2_M)) /* No config4, no DSP ASE, no large physaddr (PABITS), - no external interrupt controller, no vectored interupts, + no external interrupt controller, no vectored interrupts, no 1kb pages, no SmartMIPS ASE, no trace logic */ #define MIPS_CONFIG3 \ ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ -- cgit v1.2.3