From 1239b472bb0dba8060f1af29d40dafbc1b2860d4 Mon Sep 17 00:00:00 2001 From: Kwok Cheung Yeung Date: Fri, 17 May 2013 14:51:21 -0700 Subject: linux-user: Save the correct resume address for MIPS signal handling The current ISA mode needs to be saved in bit 0 of the resume address. If the current instruction happens to be in a branch delay slot, then the address of the preceding jump instruction should be stored instead. exception_resume_pc already does both of these tasks, so it is made available and reused. MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the first instruction of the signal handler as a delay slot instruction. Signed-off-by: Kwok Cheung Yeung Signed-off-by: Aurelien Jarno --- target-mips/cpu.h | 1 + target-mips/helper.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'target-mips') diff --git a/target-mips/cpu.h b/target-mips/cpu.h index cedf03df43..6e761e03b6 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -668,6 +668,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, int rw); #endif +target_ulong exception_resume_pc (CPUMIPSState *env); static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, target_ulong *cs_base, int *flags) diff --git a/target-mips/helper.c b/target-mips/helper.c index 3a54acf706..36929ddee7 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -366,8 +366,7 @@ static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_CACHE] = "cache error", }; -#if !defined(CONFIG_USER_ONLY) -static target_ulong exception_resume_pc (CPUMIPSState *env) +target_ulong exception_resume_pc (CPUMIPSState *env) { target_ulong bad_pc; target_ulong isa_mode; @@ -383,6 +382,7 @@ static target_ulong exception_resume_pc (CPUMIPSState *env) return bad_pc; } +#if !defined(CONFIG_USER_ONLY) static void set_hflags_for_handler (CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ -- cgit v1.2.3