From 73642f5bdb71f478f221593ec7b06c974a2cb5b6 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Tue, 15 Dec 2009 14:43:40 +0100 Subject: target-mips: 4Kc, 4KEc cores do not support MIPS16 4Kc, 4KEc cores do not support MIPS16, so not only the CP0_Config1 had to be fixed (see previous patch), but also MIPS16 instructions must not be executed. (Hint from Nathan Froyd, thanks). Signed-off-by: Stefan Weil Signed-off-by: Aurelien Jarno --- target-mips/translate_init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'target-mips/translate_init.c') diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 11bc47c0a3..dc14be504c 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -115,7 +115,7 @@ static const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x1278FF17, .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .insn_flags = CPU_MIPS32, .mmu_type = MMU_TYPE_R4000, }, { @@ -157,7 +157,7 @@ static const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x1278FF17, .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .insn_flags = CPU_MIPS32, .mmu_type = MMU_TYPE_R4000, }, { @@ -198,7 +198,7 @@ static const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x1278FF17, .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .insn_flags = CPU_MIPS32R2, .mmu_type = MMU_TYPE_R4000, }, { -- cgit v1.2.3