From a23a663b6555497b1569e407cc8edff09787decb Mon Sep 17 00:00:00 2001
From: aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Tue, 22 Apr 2008 21:57:57 +0000
Subject: Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52
 bits long. Thanks to Paul Brook for noticing that.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4242 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-i386/helper2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'target-i386')

diff --git a/target-i386/helper2.c b/target-i386/helper2.c
index d5dc96ba16..106720aa7f 100644
--- a/target-i386/helper2.c
+++ b/target-i386/helper2.c
@@ -800,7 +800,8 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 
 #else
 
-#define PHYS_ADDR_MASK (~0xfff)
+/* Bits 52-62 of a PTE are reserved. Bit 63 is the NX bit. */
+#define PHYS_ADDR_MASK 0xffffffffff000L
 
 /* return value:
    -1 = cannot handle fault
-- 
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