From b6af097528caba5b23b79db3f1f1fd08fa4fa11e Mon Sep 17 00:00:00 2001 From: "Daniel P. Berrange" Date: Wed, 26 Aug 2015 12:17:13 +0100 Subject: maint: remove / fix many doubled words MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Many source files have doubled words (eg "the the", "to to", and so on). Most of these can simply be removed, but a couple were actual mis-spellings (eg "to to" instead of "to do"). There was even one triple word score "to to to" :-) Signed-off-by: Daniel P. Berrange Reviewed-by: Marc-André Lureau Reviewed-by: Markus Armbruster Signed-off-by: Michael Tokarev --- target-arm/cpu.h | 4 ++-- target-arm/helper.c | 2 +- target-arm/translate.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'target-arm') diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4bd5dc875c..36407de6b3 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -173,7 +173,7 @@ typedef struct CPUARMState { uint32_t GE; /* cpsr[19:16] */ uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ - uint64_t daif; /* exception masks, in the bits they are in in PSTATE */ + uint64_t daif; /* exception masks, in the bits they are in PSTATE */ uint64_t elr_el[4]; /* AArch64 exception link regs */ uint64_t sp_el[4]; /* AArch64 banked stack pointers */ @@ -1488,7 +1488,7 @@ bool write_list_to_cpustate(ARMCPU *cpu); */ bool write_cpustate_to_list(ARMCPU *cpu); -/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. +/* Does the core conform to the "MicroController" profile. e.g. Cortex-M3. Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are conventional cores (ie. Application or Realtime profile). */ diff --git a/target-arm/helper.c b/target-arm/helper.c index fc4b65fd54..d453120874 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2123,7 +2123,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, } } - /* Update the masks corresponding to the the TCR bank being written + /* Update the masks corresponding to the TCR bank being written * Note that we always calculate mask and base_mask, but * they are only used for short-descriptor tables (ie if EAE is 0); * for long-descriptor tables the TCR fields are used differently diff --git a/target-arm/translate.c b/target-arm/translate.c index 0bd3d0517b..ae705775d1 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8500,7 +8500,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } /* Perform base writeback before the loaded value to ensure correct behavior with overlapping index registers. - ldrd with base writeback is is undefined if the + ldrd with base writeback is undefined if the destination and index registers overlap. */ if (!(insn & (1 << 24))) { gen_add_datah_offset(s, insn, address_offset, addr); -- cgit v1.2.3 From 67cc32ebfd8c0ee3fcdb26780a8991baf5eb1d45 Mon Sep 17 00:00:00 2001 From: Veres Lajos Date: Tue, 8 Sep 2015 22:45:14 +0100 Subject: typofixes - v4 Signed-off-by: Veres Lajos Signed-off-by: Michael Tokarev --- target-arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target-arm') diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 36407de6b3..5abd8ba5c5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -224,8 +224,8 @@ typedef struct CPUARMState { }; /* MMU translation table base control. */ TCR tcr_el[4]; - uint32_t c2_data; /* MPU data cachable bits. */ - uint32_t c2_insn; /* MPU instruction cachable bits. */ + uint32_t c2_data; /* MPU data cacheable bits. */ + uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register * MPU write buffer control. */ -- cgit v1.2.3