From 0fa85d43d47151e71e63754e419340bfcff97e80 Mon Sep 17 00:00:00 2001
From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Mon, 3 Jan 2005 23:43:32 +0000
Subject: 64 bit target support

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1195 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-arm/translate.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'target-arm')

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 56efa41e10..8ec392487e 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -29,7 +29,7 @@
 
 /* internal defines */
 typedef struct DisasContext {
-    uint8_t *pc;
+    target_ulong pc;
     int is_jmp;
     struct TranslationBlock *tb;
 } DisasContext;
@@ -762,10 +762,10 @@ static inline int gen_intermediate_code_internal(CPUState *env,
     DisasContext dc1, *dc = &dc1;
     uint16_t *gen_opc_end;
     int j, lj;
-    uint8_t *pc_start;
+    target_ulong pc_start;
     
     /* generate intermediate code */
-    pc_start = (uint8_t *)tb->pc;
+    pc_start = tb->pc;
        
     dc->tb = tb;
 
@@ -784,7 +784,7 @@ static inline int gen_intermediate_code_internal(CPUState *env,
                 while (lj < j)
                     gen_opc_instr_start[lj++] = 0;
             }
-            gen_opc_pc[lj] = (uint32_t)dc->pc;
+            gen_opc_pc[lj] = dc->pc;
             gen_opc_instr_start[lj] = 1;
         }
         disas_arm_insn(dc);
@@ -811,7 +811,7 @@ static inline int gen_intermediate_code_internal(CPUState *env,
     if (loglevel & CPU_LOG_TB_IN_ASM) {
         fprintf(logfile, "----------------\n");
         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
-        disas(logfile, pc_start, dc->pc - pc_start, 0, 0);
+        target_disas(logfile, pc_start, dc->pc - pc_start, 0);
         fprintf(logfile, "\n");
         if (loglevel & (CPU_LOG_TB_OP)) {
             fprintf(logfile, "OP:\n");
-- 
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