From 11e169de9940b9dc057e534ecf864c542fafb425 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Tue, 17 Dec 2013 19:42:32 +0000 Subject: target-arm: A64: add support for B and BL insns Implement the B and BL instructions (PC relative branches and calls). For convenience in managing TCG temporaries which might be generated if a source register is the zero-register XZR, we provide a simple mechanism for creating a new temp which is automatically freed at the end of decode of the instruction. Signed-off-by: Alexander Graf [claudio: renamed functions, adapted to new decoder layout] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target-arm/translate.h') diff --git a/target-arm/translate.h b/target-arm/translate.h index 878918176f..23a45daff8 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -24,6 +24,9 @@ typedef struct DisasContext { int vec_len; int vec_stride; int aarch64; +#define TMP_A64_MAX 16 + int tmp_a64_count; + TCGv_i64 tmp_a64[TMP_A64_MAX]; } DisasContext; extern TCGv_ptr cpu_env; -- cgit v1.2.3