From 5ce4ff6502fc6ae01a30c3917996c6c41be1d176 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 21 Jan 2016 14:15:07 +0000 Subject: target-arm: Support multiple address spaces in page table walks If we have a secure address space, use it in page table walks: when doing the physical accesses to read descriptors, make them through the correct address space. (The descriptor reads are the only direct physical accesses made in target-arm/ for CPUs which might have TrustZone.) Signed-off-by: Peter Maydell Acked-by: Edgar E. Iglesias --- target-arm/helper.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'target-arm/helper.c') diff --git a/target-arm/helper.c b/target-arm/helper.c index 16a5406e21..6c5dcfd3cf 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6273,13 +6273,15 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; MemTxAttrs attrs = {}; + AddressSpace *as; attrs.secure = is_secure; + as = arm_addressspace(cs, attrs); addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); if (fi->s1ptw) { return 0; } - return address_space_ldl(cs->as, addr, attrs, NULL); + return address_space_ldl(as, addr, attrs, NULL); } static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, @@ -6289,13 +6291,15 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; MemTxAttrs attrs = {}; + AddressSpace *as; attrs.secure = is_secure; + as = arm_addressspace(cs, attrs); addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); if (fi->s1ptw) { return 0; } - return address_space_ldq(cs->as, addr, attrs, NULL); + return address_space_ldq(as, addr, attrs, NULL); } static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, -- cgit v1.2.3