From b4d3978c2fdf944e428a46d2850dbd950b6fbe78 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 13 Aug 2015 11:26:22 +0100 Subject: target-arm: Add the AArch64 view of the Secure physical timer On CPUs with EL3, there are two physical timers, one for Secure and one for Non-secure. Implement this extra timer and the AArch64 registers which access it. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Message-id: 1437047249-2357-2-git-send-email-peter.maydell@linaro.org --- target-arm/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target-arm/cpu.h') diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ebca342e42..2e680da1fc 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -114,7 +114,8 @@ typedef struct ARMGenericTimer { #define GTIMER_PHYS 0 #define GTIMER_VIRT 1 #define GTIMER_HYP 2 -#define NUM_GTIMERS 3 +#define GTIMER_SEC 3 +#define NUM_GTIMERS 4 typedef struct { uint64_t raw_tcr; -- cgit v1.2.3