From 14ade10f840deec02d32530e5a64bd5ec275adbd Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Tue, 3 Sep 2013 20:12:10 +0100 Subject: target-arm: Add AArch64 translation stub We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode, registers look vastly different, instruction encoding is completely different, basically the system turns into a different machine. So let's do a simple if() in translate.c to decide whether we can handle the current code in the legacy AArch32 code or in the new AArch64 code. So far, the translation always complains about unallocated instructions. There is no emulator functionality in this patch! Signed-off-by: Alexander Graf Signed-off-by: John Rigby Signed-off-by: Peter Maydell Message-id: 1378235544-22290-11-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-5-git-send-email-john.rigby@linaro.org [PMM: * provide no-op versions of a64 functions ifndef TARGET_AARCH64; this lets us avoid #ifdefs in translate.c * insert the missing call to disas_a64_insn() * stash the insn in the DisasContext rather than reloading it in real_unallocated_encoding() ] Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'target-arm/cpu-qom.h') diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index fbe846e373..6502a7b7b3 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -173,4 +173,9 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); +#ifdef TARGET_AARCH64 +void aarch64_cpu_dump_state(CPUState *cs, FILE *f, + fprintf_function cpu_fprintf, int flags); +#endif + #endif -- cgit v1.2.3