From 2e211e0a12e6cde512b65d25799bb3ac25baa371 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 16 Dec 2020 12:34:42 +0100 Subject: target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210104221154.3127610-16-f4bug@amsat.org> --- linux-user/mips/cpu_loop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'linux-user/mips') diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 748e1c664f..19947448a2 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,7 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) prog_req.fre &= interp_req.fre; bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 || - env->insn_flags & ISA_MIPS32R6; + env->insn_flags & ISA_MIPS_R6; if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |= (1 << CP0C5_FRE); -- cgit v1.2.3