From 623e250abdca2c29830793e3ac81a9e405f33216 Mon Sep 17 00:00:00 2001 From: Tom Musta Date: Mon, 16 Jun 2014 11:03:19 -0500 Subject: linux-user: Correct AUXV Cache Line Sizes for PowerPC Set the AT_ICACHEBSIZE and AT_DCACHEBSIZE entries of the AUXV to match the CPU model's cache line sizes. This fixes memory clobbering problems on more recent Book 3s implementations; memset(p, 0, N) will use the dcbz instruction when N is sufficiently large and many of the newer server CPUs have cache lines sizes of 128 bytes. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- linux-user/elfload.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'linux-user/elfload.c') diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1248eda272..64d23fa647 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -774,8 +774,9 @@ static uint32_t get_elf_hwcap(void) #define DLINFO_ARCH_ITEMS 5 #define ARCH_DLINFO \ do { \ - NEW_AUX_ENT(AT_DCACHEBSIZE, 0x20); \ - NEW_AUX_ENT(AT_ICACHEBSIZE, 0x20); \ + PowerPCCPU *cpu = POWERPC_CPU(thread_cpu); \ + NEW_AUX_ENT(AT_DCACHEBSIZE, cpu->env.dcache_line_size); \ + NEW_AUX_ENT(AT_ICACHEBSIZE, cpu->env.icache_line_size); \ NEW_AUX_ENT(AT_UCACHEBSIZE, 0); \ /* \ * Now handle glibc compatibility. \ -- cgit v1.2.3