From 631adaff31d9e127fecccb4a811c20ae13cd7194 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Sat, 22 Oct 2016 11:46:38 +0200 Subject: ppc/pnv: add a PIR handler to PnvChip MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Processor Identification Register (PIR) is a register that holds a processor identifier which is used for bus transactions (XSCOM) and for processor differentiation in multiprocessor systems. It also used in the interrupt vector entries (IVE) to identify the thread serving the interrupts. P9 and P8 have some differences in the CPU PIR encoding. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Signed-off-by: David Gibson --- include/hw/ppc/pnv.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index e084a8c303..b7987f8208 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -58,6 +58,8 @@ typedef struct PnvChipClass { PnvChipType chip_type; uint64_t chip_cfam_id; uint64_t cores_mask; + + uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); } PnvChipClass; #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" -- cgit v1.2.3