From 43e3346e43f005500f1d2e44318bf8b28f0ba086 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Wed, 16 Mar 2016 17:06:00 +0000 Subject: hw/arm: Add ASPEED AST2400 SoC model While the ASPEED AST2400 SoC[1] has a broad range of capabilities this implementation is minimal, comprising an ARM926 processor, ASPEED VIC and timer devices, and a 8250 UART. [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376 Signed-off-by: Andrew Jeffery Message-id: 1458096317-25223-4-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/ast2400.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 include/hw/arm/ast2400.h (limited to 'include') diff --git a/include/hw/arm/ast2400.h b/include/hw/arm/ast2400.h new file mode 100644 index 0000000000..f16a1ed25c --- /dev/null +++ b/include/hw/arm/ast2400.h @@ -0,0 +1,35 @@ +/* + * ASPEED AST2400 SoC + * + * Andrew Jeffery + * + * Copyright 2016 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef AST2400_H +#define AST2400_H + +#include "hw/arm/arm.h" +#include "hw/intc/aspeed_vic.h" +#include "hw/timer/aspeed_timer.h" + +typedef struct AST2400State { + /*< private >*/ + DeviceState parent; + + /*< public >*/ + ARMCPU *cpu; + MemoryRegion iomem; + AspeedVICState vic; + AspeedTimerCtrlState timerctrl; +} AST2400State; + +#define TYPE_AST2400 "ast2400" +#define AST2400(obj) OBJECT_CHECK(AST2400State, (obj), TYPE_AST2400) + +#define AST2400_SDRAM_BASE 0x40000000 + +#endif /* AST2400_H */ -- cgit v1.2.3