From 04f2a8bbc019ad858cd7ec4f89b34e15f96eef4e Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Thu, 24 Jun 2021 18:50:21 +0800 Subject: tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32 Implement tcg_gen_vec_shl{shr}{sar}16i_tl by adding corresponging i32 OP. Signed-off-by: LIU Zhiwei Message-Id: <20210624105023.3852-4-zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/tcg') diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index 2d5ad6ce12..e3c9f45926 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -408,16 +408,26 @@ void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); +void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); + #if TARGET_LONG_BITS == 64 #define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i64 #define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i64 #define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64 #define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i64 +#define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i64 +#define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i64 +#define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i64 #else #define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i32 #define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i32 #define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32 #define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i32 +#define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i32 +#define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i32 +#define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i32 #endif #endif -- cgit v1.2.3