From 3222165dcb7ec2d390e400d5c886d67b582f37d7 Mon Sep 17 00:00:00 2001 From: Troy Lee Date: Tue, 11 Jan 2022 16:45:46 +0800 Subject: hw/arm/aspeed: Add the i3c device to the AST2600 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the new i3c device to the AST2600 SoC. Signed-off-by: Troy Lee Reviewed-by: Graeme Gregory Reviewed-by: Cédric Le Goater Tested-by: Graeme Gregory Message-id: 20220111084546.4145785-3-troy_lee@aspeedtech.com [PMM: tidied commit message] Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/hw') diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 18fb7eed46..cae9906684 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -21,6 +21,7 @@ #include "hw/timer/aspeed_timer.h" #include "hw/rtc/aspeed_rtc.h" #include "hw/i2c/aspeed_i2c.h" +#include "hw/misc/aspeed_i3c.h" #include "hw/ssi/aspeed_smc.h" #include "hw/misc/aspeed_hace.h" #include "hw/watchdog/wdt_aspeed.h" @@ -51,6 +52,7 @@ struct AspeedSoCState { AspeedRtcState rtc; AspeedTimerCtrlState timerctrl; AspeedI2CState i2c; + AspeedI3CState i3c; AspeedSCUState scu; AspeedHACEState hace; AspeedXDMAState xdma; @@ -141,6 +143,7 @@ enum { ASPEED_DEV_HACE, ASPEED_DEV_DPMCU, ASPEED_DEV_DP, + ASPEED_DEV_I3C, }; #endif /* ASPEED_SOC_H */ -- cgit v1.2.3