From fadefada4d07a3a77c4171244cded0e9af81331c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 25 Sep 2019 16:32:32 +0200 Subject: aspeed/timer: Add support for IRQ status register on the AST2600 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The AST2600 timer replaces control register 2 with a interrupt status register. It is set by hardware when an IRQ occurs and cleared by software. Modify the vmstate version to take into account the new fields. Based on previous work from Joel Stanley. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-id: 20190925143248.10000-8-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/timer/aspeed_timer.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/timer/aspeed_timer.h') diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h index 69b1377af0..948329893c 100644 --- a/include/hw/timer/aspeed_timer.h +++ b/include/hw/timer/aspeed_timer.h @@ -60,6 +60,7 @@ typedef struct AspeedTimerCtrlState { uint32_t ctrl; uint32_t ctrl2; uint32_t ctrl3; + uint32_t irq_sts; AspeedTimer timers[ASPEED_TIMER_NR_TIMERS]; AspeedSCUState *scu; -- cgit v1.2.3