From 24bd283bccb334109f112839ab6867f0192045d6 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Wed, 17 Apr 2024 14:50:13 +1000 Subject: ppc/pnv: Implement ADU access to LPC space MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit One of the functions of the ADU is indirect memory access engines that send and receive data via ADU registers. This implements the ADU LPC memory access functionality sufficiently for IBM proprietary firmware to access the UART and print characters to the serial port as it does on real hardware. This requires a linkage between adu and lpc, which allows adu to perform memory access in the lpc space. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_lpc.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/hw/ppc/pnv_lpc.h') diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index e0fd5e4130..174add4c53 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -109,6 +109,11 @@ struct PnvLpcClass { DeviceRealize parent_realize; }; +bool pnv_lpc_opb_read(PnvLpcController *lpc, uint32_t addr, + uint8_t *data, int sz); +bool pnv_lpc_opb_write(PnvLpcController *lpc, uint32_t addr, + uint8_t *data, int sz); + ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp); int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr, uint64_t lpcm_size); -- cgit v1.2.3