From 920557971b60e53c2f3f22e5d6c620ab1ed411fd Mon Sep 17 00:00:00 2001 From: Paulo Alcantara Date: Sun, 28 Jun 2015 14:58:56 -0300 Subject: ich9: add TCO interface emulation This interface provides some registers within a 32-byte range and can be acessed through PCI-to-LPC bridge interface (PMBASE + 0x60). It's commonly used as a watchdog timer to detect system lockups through SMIs that are generated -- if TCO_EN bit is set -- on every timeout. If NO_REBOOT bit is not set in GCS (General Control and Status register), the system will be resetted upon second timeout if TCO_RLD register wasn't previously written to prevent timeout. This patch adds support to TCO watchdog logic and few other features like mapping NMIs to SMIs (NMI2SMI_EN bit), system intruder detection, etc. are not implemented yet. Signed-off-by: Paulo Alcantara Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/i386/ich9.h | 11 ++++++++++- include/hw/i386/pc.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include/hw/i386') diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index b317a481c8..ecb3b1038c 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -17,9 +17,12 @@ void ich9_lpc_set_irq(void *opaque, int irq_num, int level); int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx); PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin); -void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled); +void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled, bool enable_tco); I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base); +void ich9_generate_smi(void); +void ich9_generate_nmi(void); + #define ICH9_CC_SIZE (16 * 1024) /* 16KB */ #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" @@ -90,6 +93,9 @@ Object *ich9_lpc_find(void); #define ICH9_CC_DIR_MASK 0x7 #define ICH9_CC_OIC 0x31FF #define ICH9_CC_OIC_AEN 0x1 +#define ICH9_CC_GCS 0x3410 +#define ICH9_CC_GCS_DEFAULT 0x00000020 +#define ICH9_CC_GCS_NO_REBOOT (1 << 5) /* D28:F[0-5] */ #define ICH9_PCIE_DEV 28 @@ -186,7 +192,10 @@ Object *ich9_lpc_find(void); #define ICH9_PMIO_GPE0_LEN 16 #define ICH9_PMIO_SMI_EN 0x30 #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) +#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) #define ICH9_PMIO_SMI_STS 0x34 +#define ICH9_PMIO_TCO_RLD 0x60 +#define ICH9_PMIO_TCO_LEN 32 /* FADT ACPI_ENABLE/ACPI_DISABLE */ #define ICH9_APM_ACPI_ENABLE 0x2 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 786a1d511c..f9df68e0bb 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -88,6 +88,7 @@ typedef struct PcPciInfo { #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base" #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk" #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len" +#define ACPI_PM_PROP_TCO_ENABLED "enable_tco" struct PcGuestInfo { bool isapc_ram_fw; -- cgit v1.2.3 From 5add35bec1e249bb5345a47008c8f298d4760be4 Mon Sep 17 00:00:00 2001 From: Paulo Alcantara Date: Sun, 28 Jun 2015 14:58:58 -0300 Subject: ich9: implement strap SPKR pin logic If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode (ICH9 will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO_REBOOT bit (CC: offset 0x3410:bit 5). The NO_REBOOT bit is set when SPKR pin on ICH9 is sampled high. This bit may be set or cleared by software if the strap is sampled low but may not override the strap when it indicates "No Reboot". This patch implements the logic where hardware has ability to set SPKR pin through a property named "noreboot" and it's sampled high by default. Signed-off-by: Paulo Alcantara Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/i386/ich9.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/hw/i386') diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index ecb3b1038c..b9d2b04b6e 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -46,6 +46,11 @@ typedef struct ICH9LPCState { ICH9LPCPMRegs pm; uint32_t sci_level; /* track sci level */ + /* 2.24 Pin Straps */ + struct { + bool spkr_hi; + } pin_strap; + /* 10.1 Chipset Configuration registers(Memory Space) which is pointed by RCBA */ uint8_t chip_config[ICH9_CC_SIZE]; -- cgit v1.2.3 From 220a8846429ac954932e16010efb07af0aba4529 Mon Sep 17 00:00:00 2001 From: Laszlo Ersek Date: Thu, 25 Jun 2015 15:35:07 +0200 Subject: hw/i386/pc: don't carry FDC from pc_basic_device_init() to pc_cmos_init() Thanks to the last patch, pc_cmos_init() doesn't need the (optional) board-default FDC any longer as an input parameter. Update pc_basic_device_init() not to hand it back to pc_init1() / pc_q35_init(), and update the latter not to carry the FDC to pc_cmos_init(). This simplifies the code. pc_init1() | pc_q35_init() pc_basic_device_init() pc_cmos_init() Cc: Jan Tomko Cc: John Snow Cc: Markus Armbruster Cc: Paolo Bonzini Signed-off-by: Laszlo Ersek Reviewed-by: John Snow Reviewed-by: Markus Armbruster Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/i386/pc.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include/hw/i386') diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index f9df68e0bb..954e2681be 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -199,13 +199,12 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, ISADevice **rtc_state, bool create_fdctrl, - ISADevice **floppy, bool no_vmport, uint32 hpet_irqs); void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, const char *boot_device, MachineState *machine, - ISADevice *floppy, BusState *ide0, BusState *ide1, + BusState *ide0, BusState *ide1, ISADevice *s); void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_pci_device_init(PCIBus *pci_bus); -- cgit v1.2.3