From 94500e83eaf4a577ee4ce5ce16be0587ed04a225 Mon Sep 17 00:00:00 2001 From: Jamin Lin Date: Tue, 3 Sep 2024 16:35:18 +0800 Subject: hw/i2c/aspeed: Support discontinuous register memory region of I2C bus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It only support continuous register memory region for all I2C bus. However, the register address of all I2c bus are discontinuous for AST2700. Ex: the register address of I2C bus for ast2700 as following. 0x100 - 0x17F: Device 0 0x200 - 0x27F: Device 1 0x300 - 0x37F: Device 2 0x400 - 0x47F: Device 3 0x500 - 0x57F: Device 4 0x600 - 0x67F: Device 5 0x700 - 0x77F: Device 6 0x800 - 0x87F: Device 7 0x900 - 0x97F: Device 8 0xA00 - 0xA7F: Device 9 0xB00 - 0xB7F: Device 10 0xC00 - 0xC7F: Device 11 0xD00 - 0xD7F: Device 12 0xE00 - 0xE7F: Device 13 0xF00 – 0xF7F: Device 14 0x1000 – 0x107F: Device 15 Introduce a new class attribute to make user set each I2C bus gap size. Update formula to create all I2C bus register memory regions. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- include/hw/i2c/aspeed_i2c.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/i2c') diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index fad5e9259a..02ede85906 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -275,6 +275,7 @@ struct AspeedI2CClass { uint8_t num_busses; uint8_t reg_size; + uint32_t reg_gap_size; uint8_t gap; qemu_irq (*bus_get_irq)(AspeedI2CBus *); -- cgit v1.2.3 From 62c0c65d4fee467050eea52fe5d2e5a7891e9764 Mon Sep 17 00:00:00 2001 From: Jamin Lin Date: Tue, 3 Sep 2024 16:35:19 +0800 Subject: hw/i2c/aspeed: Introduce a new bus pool buffer attribute in AspeedI2Cbus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the datasheet of ASPEED SOCs, each I2C bus has their own pool buffer since AST2500. Only AST2400 utilized a pool buffer share to all I2C bus. Besides, using a share pool buffer only support pool buffer memory regions are continuous for all I2C bus. To make this model more readable and support discontinuous bus pool buffer memory regions, changes to introduce a new bus pool buffer attribute in AspeedI2Cbus and new memops. So, it does not need to calculate the pool buffer offset for different I2C bus. Introduce a new has_share_pool class attribute in AspeedI2CClass and use it to create either a share pool buffer or bus pool buffers in aspeed_i2c_realize. Update each pull buffer size to 0x10 for AST2500 and 0x20 for AST2600 and AST1030. Incrementing the version of aspeed_i2c_bus_vmstate to 6. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- include/hw/i2c/aspeed_i2c.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/hw/i2c') diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 02ede85906..8e62ec64f8 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -35,6 +35,7 @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) #define ASPEED_I2C_NR_BUSSES 16 #define ASPEED_I2C_SHARE_POOL_SIZE 0x800 +#define ASPEED_I2C_BUS_POOL_SIZE 0x20 #define ASPEED_I2C_OLD_NUM_REG 11 #define ASPEED_I2C_NEW_NUM_REG 22 @@ -239,12 +240,14 @@ struct AspeedI2CBus { I2CSlave *slave; MemoryRegion mr; + MemoryRegion mr_pool; I2CBus *bus; uint8_t id; qemu_irq irq; uint32_t regs[ASPEED_I2C_NEW_NUM_REG]; + uint8_t pool[ASPEED_I2C_BUS_POOL_SIZE]; }; struct AspeedI2CState { @@ -284,6 +287,7 @@ struct AspeedI2CClass { uint8_t *(*bus_pool_base)(AspeedI2CBus *); bool check_sram; bool has_dma; + bool has_share_pool; uint64_t mem_size; }; -- cgit v1.2.3 From d46a4ba0f4e331ff21a82863a3d96a5cd8849025 Mon Sep 17 00:00:00 2001 From: Jamin Lin Date: Tue, 3 Sep 2024 16:35:20 +0800 Subject: hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C bus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It only support continuous pool buffer memory region for all I2C bus. However, the pool buffer address of all I2c bus are discontinuous for AST2700. Ex: the pool buffer address of I2C bus for ast2700 as following. 0x1A0 - 0x1BF: Device 0 buffer 0x2A0 - 0x2BF: Device 1 buffer 0x3A0 - 0x3BF: Device 2 buffer 0x4A0 - 0x4BF: Device 3 buffer 0x5A0 - 0x5BF: Device 4 buffer 0x6A0 - 0x6BF: Device 5 buffer 0x7A0 - 0x7BF: Device 6 buffer 0x8A0 - 0x8BF: Device 7 buffer 0x9A0 - 0x9BF: Device 8 buffer 0xAA0 - 0xABF: Device 9 buffer 0xBA0 - 0xBBF: Device 10 buffer 0xCA0 - 0xCBF: Device 11 buffer 0xDA0 - 0xDBF: Device 12 buffer 0xEA0 - 0xEBF: Device 13 buffer 0xFA0 – 0xFBF: Device 14 buffer 0x10A0 – 0x10BF: Device 15 buffer Introduce a new class attribute to make user set each I2C bus pool buffer gap size. Update formula to create all I2C bus pool buffer memory regions. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- include/hw/i2c/aspeed_i2c.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/i2c') diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 8e62ec64f8..b42c4dc584 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -284,6 +284,7 @@ struct AspeedI2CClass { uint64_t pool_size; hwaddr pool_base; + uint32_t pool_gap_size; uint8_t *(*bus_pool_base)(AspeedI2CBus *); bool check_sram; bool has_dma; -- cgit v1.2.3 From c400c38854017eeccda63115814eba4c3ef2b51f Mon Sep 17 00:00:00 2001 From: Jamin Lin Date: Tue, 3 Sep 2024 16:35:21 +0800 Subject: hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The "Current DMA Operating Address Status(0x50)" register of I2C new mode has been removed in AST2700. This register is used for debugging and it is a read only register. To support AST2700 DMA mode, introduce a new dma_dram_offset class attribute in AspeedI2Cbus to save the current DMA operating address. ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 00000000" which is 64bits address. Set the dma_dram_offset data type to uint64_t for 64 bits dram address DMA support. Both "DMA Mode Buffer Address Register(I2CD24 old mode)" and "DMA Operating Address Status (I2CC50 new mode)" are used for showing the low part dram offset bits [31:0], so change to read/write both register bits [31:0] in bus register read/write functions. The aspeed_i2c_bus_vmstate is changed again and version is not increased because it was done earlier in the same series. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- include/hw/i2c/aspeed_i2c.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'include/hw/i2c') diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index b42c4dc584..bdaea3207d 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -248,6 +248,7 @@ struct AspeedI2CBus { uint32_t regs[ASPEED_I2C_NEW_NUM_REG]; uint8_t pool[ASPEED_I2C_BUS_POOL_SIZE]; + uint64_t dma_dram_offset; }; struct AspeedI2CState { @@ -369,14 +370,6 @@ static inline uint32_t aspeed_i2c_bus_dma_len_offset(AspeedI2CBus *bus) return R_I2CD_DMA_LEN; } -static inline uint32_t aspeed_i2c_bus_dma_addr_offset(AspeedI2CBus *bus) -{ - if (aspeed_i2c_is_new_mode(bus->controller)) { - return R_I2CC_DMA_ADDR; - } - return R_I2CD_DMA_ADDR; -} - static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) { return SHARED_ARRAY_FIELD_EX32(bus->regs, aspeed_i2c_bus_ctrl_offset(bus), -- cgit v1.2.3 From 1809ab6a67359e0876981cd05d2a50b2843eabad Mon Sep 17 00:00:00 2001 From: Jamin Lin Date: Tue, 3 Sep 2024 16:35:22 +0800 Subject: hw/i2c/aspeed: Add AST2700 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce a new ast2700 class to support AST2700. The I2C bus register memory regions and I2C bus pool buffer memory regions are discontinuous and they do not back compatible AST2600. Add a new ast2700 i2c class init function to match the address of I2C bus register and pool buffer from the datasheet. An I2C controller registers owns 8KB address space. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- include/hw/i2c/aspeed_i2c.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/i2c') diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index bdaea3207d..4f23dc10c3 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -31,6 +31,7 @@ #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600" #define TYPE_ASPEED_1030_I2C TYPE_ASPEED_I2C "-ast1030" +#define TYPE_ASPEED_2700_I2C TYPE_ASPEED_I2C "-ast2700" OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) #define ASPEED_I2C_NR_BUSSES 16 -- cgit v1.2.3 From 3dbab141d5c51de97cf514f0b6187f5f54fd922c Mon Sep 17 00:00:00 2001 From: Jamin Lin Date: Tue, 3 Sep 2024 16:35:23 +0800 Subject: hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) and the base address of dram is "0x4 00000000" which is 64bits address. It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)" registers to save the high part physical address of Tx/Rx buffer address for master mode. It has "Slave DMA Mode Tx Buffer Base Address[39:32](0x68)" and "Slave DMA Mode Rx Buffer Base Address[39:32](0x6C)" registers to save the high part physical address of Tx/Rx buffer address for slave mode. Ex: Tx buffer address for master mode [39:0] The "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" bits [7:0] which corresponds the bits [39:32] of the 64 bits address of the Tx buffer address. The "Master DMA Mode Tx Buffer Base Address(0x30)" bits [31:0] which corresponds the bits [31:0] of the 64 bits address of the Tx buffer address. Introduce a new has_dma64 class attribute and new registers for the new mode to support DMA 64 bits dram address. Update new mode register number to 28. The aspeed_i2c_bus_vmstate is changed again and version is not increased because it was done earlier in the same series. Signed-off-by: Jamin Lin --- include/hw/i2c/aspeed_i2c.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'include/hw/i2c') diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 4f23dc10c3..2c4c81bd20 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -38,7 +38,7 @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) #define ASPEED_I2C_SHARE_POOL_SIZE 0x800 #define ASPEED_I2C_BUS_POOL_SIZE 0x20 #define ASPEED_I2C_OLD_NUM_REG 11 -#define ASPEED_I2C_NEW_NUM_REG 22 +#define ASPEED_I2C_NEW_NUM_REG 28 #define A_I2CD_M_STOP_CMD BIT(5) #define A_I2CD_M_RX_CMD BIT(3) @@ -227,6 +227,15 @@ REG32(I2CS_DMA_LEN_STS, 0x4c) FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13) REG32(I2CC_DMA_ADDR, 0x50) REG32(I2CC_DMA_LEN, 0x54) +/* DMA 64bits */ +REG32(I2CM_DMA_TX_ADDR_HI, 0x60) + FIELD(I2CM_DMA_TX_ADDR_HI, ADDR_HI, 0, 7) +REG32(I2CM_DMA_RX_ADDR_HI, 0x64) + FIELD(I2CM_DMA_RX_ADDR_HI, ADDR_HI, 0, 7) +REG32(I2CS_DMA_TX_ADDR_HI, 0x68) + FIELD(I2CS_DMA_TX_ADDR_HI, ADDR_HI, 0, 7) +REG32(I2CS_DMA_RX_ADDR_HI, 0x6c) + FIELD(I2CS_DMA_RX_ADDR_HI, ADDR_HI, 0, 7) struct AspeedI2CState; @@ -292,6 +301,7 @@ struct AspeedI2CClass { bool has_dma; bool has_share_pool; uint64_t mem_size; + bool has_dma64; }; static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s) -- cgit v1.2.3