From a41d3aae52c6b1657f665fcd26d122b0646cd330 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:23 +0200 Subject: cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-7-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 33 ++++----------------------------- 1 file changed, 4 insertions(+), 29 deletions(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index d45f78290e..df49528785 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -586,18 +586,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags); * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs) -{ - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); - } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs = MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); -} +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * cpu_get_phys_page_debug: @@ -609,12 +599,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) -{ - MemTxAttrs attrs = {}; - - return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); -} +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); /** cpu_asidx_from_attrs: * @cpu: CPU @@ -623,17 +608,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) * Returns the address space index specifying the CPU AddressSpace * to use for a memory access with the given transaction attributes. */ -static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) -{ - CPUClass *cc = CPU_GET_CLASS(cpu); - int ret = 0; - - if (cc->asidx_from_attrs) { - ret = cc->asidx_from_attrs(cpu, attrs); - assert(ret < cpu->num_ases && ret >= 0); - } - return ret; -} +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); #endif /* CONFIG_USER_ONLY */ -- cgit v1.2.3 From cdba7e2f497d3922a6934b7504925483b32c0a74 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:24 +0200 Subject: cpu: Introduce cpu_virtio_is_big_endian() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce the cpu_virtio_is_big_endian() generic helper to avoid calling CPUClass internal virtio_is_big_endian() one. Similarly to commit bf7663c4bd8 ("cpu: introduce CPUClass::virtio_is_big_endian()"), we keep 'virtio' in the method name to hint this handler shouldn't be called anywhere but from the virtio code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-8-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index df49528785..d96ff4dace 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -610,6 +610,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); */ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); +/** + * cpu_virtio_is_big_endian: + * @cpu: CPU + + * Returns %true if a CPU which supports runtime configurable endianness + * is currently big-endian. + */ +bool cpu_virtio_is_big_endian(CPUState *cpu); + #endif /* CONFIG_USER_ONLY */ /** -- cgit v1.2.3 From 744c72a837a0428f2d5373793e42aba963bf47c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:29 +0200 Subject: cpu: Rename CPUClass vmsd -> legacy_vmsd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Quoting Peter Maydell [*]: There are two ways to handle migration for a CPU object: (1) like any other device, so it has a dc->vmsd that covers migration for the whole object. As usual for objects that are a subclass of a parent that has state, the first entry in the VMStateDescription field list is VMSTATE_CPU(), which migrates the cpu_common fields, followed by whatever the CPU's own migration fields are. (2) a backwards-compatible mechanism for CPUs that were originally migrated using manual "write fields to the migration stream structures". The on-the-wire migration format for those is based on the 'env' pointer (which isn't a QOM object), and the cpu_common part of the migration data is elsewhere. cpu_exec_realizefn() handles both possibilities: * for type 1, dc->vmsd is set and cc->vmsd is not, so cpu_exec_realizefn() does nothing, and the standard "register dc->vmsd for a device" code does everything needed * for type 2, dc->vmsd is NULL and so we register the vmstate_cpu_common directly to handle the cpu-common fields, and the cc->vmsd to handle the per-CPU stuff You can't change a CPU from one type to the other without breaking migration compatibility, which is why some guest architectures are stuck on the cc->vmsd form. New targets should use dc->vmsd. To avoid new targets to start using type (2), rename cc->vmsd as cc->legacy_vmsd. The correct field to implement is dc->vmsd (the DeviceClass one). See also commit b170fce3dd0 ("cpu: Register VMStateDescription through CPUState") for historic background. [*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Cc: Peter Maydell Message-Id: <20210517105140.1062037-13-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index d96ff4dace..1dfb788415 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -122,7 +122,8 @@ struct AccelCPUClass; * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @vmsd: State description for migration. + * @legacy_vmsd: Legacy state description for migration. + * Do not use in new targets, use #DeviceClass::vmsd instead. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop @@ -177,7 +178,7 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); - const VMStateDescription *vmsd; + const VMStateDescription *legacy_vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); -- cgit v1.2.3 From 8b80bd28a5cf8d8af7d38abcf1c7d81a1b226ec3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:31 +0200 Subject: cpu: Introduce SysemuCPUOps structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce a structure to hold handler specific to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-15-f4bug@amsat.org> [rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch] Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 6 ++++++ include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 include/hw/core/sysemu-cpu-ops.h (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1dfb788415..cd3fb70cb5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,6 +80,9 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; +/* see sysemu-cpu-ops.h */ +struct SysemuCPUOps; + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -191,6 +194,9 @@ struct CPUClass { bool gdb_stop_before_watchpoint; struct AccelCPUClass *accel_cpu; + /* when system emulation is not available, this pointer is NULL */ + const struct SysemuCPUOps *sysemu_ops; + /* when TCG is not available, this pointer is NULL */ struct TCGCPUOps *tcg_ops; diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h new file mode 100644 index 0000000000..e54a08ea25 --- /dev/null +++ b/include/hw/core/sysemu-cpu-ops.h @@ -0,0 +1,21 @@ +/* + * CPU operations specific to system emulation + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef SYSEMU_CPU_OPS_H +#define SYSEMU_CPU_OPS_H + +#include "hw/core/cpu.h" + +/* + * struct SysemuCPUOps: System operations specific to a CPU class + */ +typedef struct SysemuCPUOps { +} SysemuCPUOps; + +#endif /* SYSEMU_CPU_OPS_H */ -- cgit v1.2.3 From feece4d07021576a6037adfd597598851cf32bf0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:32 +0200 Subject: cpu: Move CPUClass::vmsd to SysemuCPUOps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Migration is specific to system emulation. - Move the CPUClass::vmsd field to SysemuCPUOps, - restrict VMSTATE_CPU() macro to sysemu, - vmstate_dummy is now unused, remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-16-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 8 ++------ include/hw/core/sysemu-cpu-ops.h | 6 ++++++ 2 files changed, 8 insertions(+), 6 deletions(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index cd3fb70cb5..c8d4a8a642 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -125,8 +125,6 @@ struct SysemuCPUOps; * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @legacy_vmsd: Legacy state description for migration. - * Do not use in new targets, use #DeviceClass::vmsd instead. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop @@ -181,7 +179,6 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); - const VMStateDescription *legacy_vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); @@ -1065,10 +1062,8 @@ bool target_words_bigendian(void); #ifdef NEED_CPU_H #ifdef CONFIG_SOFTMMU + extern const VMStateDescription vmstate_cpu_common; -#else -#define vmstate_cpu_common vmstate_dummy -#endif #define VMSTATE_CPU() { \ .name = "parent_obj", \ @@ -1077,6 +1072,7 @@ extern const VMStateDescription vmstate_cpu_common; .flags = VMS_STRUCT, \ .offset = 0, \ } +#endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index e54a08ea25..0370ac1519 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,12 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @legacy_vmsd: Legacy state for migration. + * Do not use in new targets, use #DeviceClass::vmsd instead. + */ + const VMStateDescription *legacy_vmsd; + } SysemuCPUOps; #endif /* SYSEMU_CPU_OPS_H */ -- cgit v1.2.3 From da383e0263f7d711eddd4f050ca95fd5ab8d2a87 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:33 +0200 Subject: cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit VirtIO devices are only meaningful with system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-17-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 5 ----- include/hw/core/sysemu-cpu-ops.h | 9 +++++++++ 2 files changed, 9 insertions(+), 5 deletions(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c8d4a8a642..dd3f5f996e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -90,10 +90,6 @@ struct SysemuCPUOps; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @virtio_is_big_endian: Callback to return %true if a CPU which supports - * runtime configurable endianness is currently big-endian. Non-configurable - * CPUs can use the default implementation of this method. This method should - * not be used by any callers other than the pre-1.0 virtio devices. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. @@ -152,7 +148,6 @@ struct CPUClass { int reset_dump_flags; bool (*has_work)(CPUState *cpu); - bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index 0370ac1519..8fa98bf2a7 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,15 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @virtio_is_big_endian: Callback to return %true if a CPU which supports + * runtime configurable endianness is currently big-endian. + * Non-configurable CPUs can use the default implementation of this method. + * This method should not be used by any callers other than the pre-1.0 + * virtio devices. + */ + bool (*virtio_is_big_endian)(CPUState *cpu); + /** * @legacy_vmsd: Legacy state for migration. * Do not use in new targets, use #DeviceClass::vmsd instead. -- cgit v1.2.3 From 83ec01b675a731910b3b2183091302ad31b3482b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:34 +0200 Subject: cpu: Move CPUClass::get_crash_info to SysemuCPUOps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit cpu_get_crash_info() is called on GUEST_PANICKED events, which only occur in system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-18-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 - include/hw/core/sysemu-cpu-ops.h | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index dd3f5f996e..bf7d11b14f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -151,7 +151,6 @@ struct CPUClass { int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); - GuestPanicInformation* (*get_crash_info)(CPUState *cpu); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index 8fa98bf2a7..b9383101fc 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_crash_info: Callback for reporting guest crash information in + * GUEST_PANICKED events. + */ + GuestPanicInformation* (*get_crash_info)(CPUState *cpu); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. -- cgit v1.2.3 From 715e3c1afb0022fb2e0f60a198ed2c740e3c48f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:35 +0200 Subject: cpu: Move CPUClass::write_elf* to SysemuCPUOps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The write_elf*() handlers are used to dump vmcore images. This feature is only meaningful for system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-19-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 17 ----------------- include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++ 2 files changed, 24 insertions(+), 17 deletions(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bf7d11b14f..15b16d3f6d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -113,14 +113,6 @@ struct SysemuCPUOps; * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. - * @write_elf64_note: Callback for writing a CPU-specific ELF note to a - * 64-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. - * @write_elf32_note: Callback for writing a CPU-specific ELF note to a - * 32-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop @@ -164,15 +156,6 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); - int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index b9383101fc..52ac0ae4e1 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,30 @@ typedef struct SysemuCPUOps { * GUEST_PANICKED events. */ GuestPanicInformation* (*get_crash_info)(CPUState *cpu); + /** + * @write_elf32_note: Callback for writing a CPU-specific ELF note to a + * 32-bit VM coredump. + */ + int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf64_note: Callback for writing a CPU-specific ELF note to a + * 64-bit VM coredump. + */ + int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF + * note to a 32-bit VM coredump. + */ + int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); + /** + * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specific ELF + * note to a 64-bit VM coredump. + */ + int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. -- cgit v1.2.3 From faf39e828374d83ca82b02c0c25cdeca9ce9581e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:36 +0200 Subject: cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-20-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 15b16d3f6d..af6246c905 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -109,8 +109,6 @@ struct SysemuCPUOps; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. - * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for - * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -152,7 +150,6 @@ struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); - int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index 52ac0ae4e1..8f8326e810 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for + * a memory access with the specified memory transaction attributes. + */ + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); /** * @get_crash_info: Callback for reporting guest crash information in * GUEST_PANICKED events. -- cgit v1.2.3 From 08928c6d0db7d554ef041256e52330bb257bc70f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:37 +0200 Subject: cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-21-f4bug@amsat.org> [rth: Drop declaration movement from target/*/cpu.h] Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 8 -------- include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++ 2 files changed, 13 insertions(+), 8 deletions(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index af6246c905..405d1f367f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -104,11 +104,6 @@ struct SysemuCPUOps; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @get_phys_page_debug: Callback for obtaining a physical address. - * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the - * associated memory transaction attributes to use for the access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -147,9 +142,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index 8f8326e810..1f249e0f06 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,19 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_phys_page_debug: Callback for obtaining a physical address. + */ + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + /** + * @get_phys_page_attrs_debug: Callback for obtaining a physical address + * and the associated memory transaction attributes to use for the + * access. + * CPUs which use memory transaction attributes should implement this + * instead of get_phys_page_debug. + */ + hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for * a memory access with the specified memory transaction attributes. -- cgit v1.2.3 From 2b60b62e05893de9698aa4a2c27de244870f0a50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:38 +0200 Subject: cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-22-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 405d1f367f..4f6dd24112 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -95,7 +95,6 @@ struct SysemuCPUOps; * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_paging_enabled: Callback for inquiring whether paging is enabled. - * @get_memory_mapping: Callback for obtaining the memory mappings. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -139,8 +138,6 @@ struct CPUClass { void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); - void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, - Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index 1f249e0f06..213e5287ab 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_memory_mapping: Callback for obtaining the memory mappings. + */ + void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, + Error **errp); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ -- cgit v1.2.3 From 6bc0d6a04733cb39d2d2bf3380a857709113242f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 17 May 2021 12:51:39 +0200 Subject: cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210517105140.1062037-23-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 2 -- include/hw/core/sysemu-cpu-ops.h | 4 ++++ 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 4f6dd24112..e4328de8d4 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -94,7 +94,6 @@ struct SysemuCPUOps; * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. - * @get_paging_enabled: Callback for inquiring whether paging is enabled. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -137,7 +136,6 @@ struct CPUClass { void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); - bool (*get_paging_enabled)(const CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index 213e5287ab..a9ba39e5f2 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,10 @@ typedef struct SysemuCPUOps { */ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); + /** + * @get_paging_enabled: Callback for inquiring whether paging is enabled. + */ + bool (*get_paging_enabled)(const CPUState *cpu); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ -- cgit v1.2.3 From 119065574d02deffc28fe5b6a864db9b467c6ffd Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 27 Feb 2021 15:21:17 -0800 Subject: hw/core: Constify TCGCPUOps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We no longer have any runtime modifications to this struct, so declare them all const. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org> --- include/hw/core/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/hw/core') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e4328de8d4..9f09a60fbd 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -156,7 +156,7 @@ struct CPUClass { const struct SysemuCPUOps *sysemu_ops; /* when TCG is not available, this pointer is NULL */ - struct TCGCPUOps *tcg_ops; + const struct TCGCPUOps *tcg_ops; /* * if not NULL, this is called in order for the CPUClass to initialize -- cgit v1.2.3