From b71d0385e97e230b45a88c604756c44a748736fb Mon Sep 17 00:00:00 2001 From: Niek Linnenbank Date: Wed, 11 Mar 2020 23:18:47 +0100 Subject: hw/arm/allwinner-h3: add SDRAM controller device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the Allwinner H3 SoC the SDRAM controller is responsible for interfacing with the external Synchronous Dynamic Random Access Memory (SDRAM). Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner H3 SDRAM controller. Signed-off-by: Niek Linnenbank Reviewed-by: Alex Bennée Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell --- include/hw/arm/allwinner-h3.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/hw/arm') diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index d338003724..065d020c73 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -41,6 +41,7 @@ #include "hw/intc/arm_gic.h" #include "hw/misc/allwinner-h3-ccu.h" #include "hw/misc/allwinner-cpucfg.h" +#include "hw/misc/allwinner-h3-dramc.h" #include "hw/misc/allwinner-h3-sysctrl.h" #include "hw/misc/allwinner-sid.h" #include "hw/sd/allwinner-sdhost.h" @@ -80,6 +81,9 @@ enum { AW_H3_UART2, AW_H3_UART3, AW_H3_EMAC, + AW_H3_DRAMCOM, + AW_H3_DRAMCTL, + AW_H3_DRAMPHY, AW_H3_GIC_DIST, AW_H3_GIC_CPU, AW_H3_GIC_HYP, @@ -120,6 +124,7 @@ typedef struct AwH3State { AwA10PITState timer; AwH3ClockCtlState ccu; AwCpuCfgState cpucfg; + AwH3DramCtlState dramc; AwH3SysCtrlState sysctrl; AwSidState sid; AwSdHostState mmc0; -- cgit v1.2.3