From 289251b033979234ed735a7b996a187880ed090e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 25 Sep 2019 16:32:47 +0200 Subject: aspeed: add support for the Aspeed MII controller of the AST2600 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The AST2600 SoC has an extra controller to set the PHY registers. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-id: 20190925143248.10000-23-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/hw/arm') diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 088a5d1081..43478f6178 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -52,6 +52,7 @@ typedef struct AspeedSoCState { AspeedSDMCState sdmc; AspeedWDTState wdt[ASPEED_WDTS_NUM]; FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; + AspeedMiiState mii[ASPEED_MACS_NUM]; AspeedGPIOState gpio; AspeedGPIOState gpio_1_8v; AspeedSDHCIState sdhci; @@ -117,6 +118,10 @@ enum { ASPEED_ETH2, ASPEED_ETH3, ASPEED_ETH4, + ASPEED_MII1, + ASPEED_MII2, + ASPEED_MII3, + ASPEED_MII4, ASPEED_SDRAM, ASPEED_XDMA, }; -- cgit v1.2.3