From 7729e1f4b3c670eca38cc0ee0d96c1177efbc1e3 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Thu, 14 May 2015 19:23:01 -0700 Subject: arm: xlnx-zynqmp: Add GIC Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: Peter Crosthwaite Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include/hw/arm/xlnx-zynqmp.h') diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 62f6b6fd65..719bc8b3ef 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -19,6 +19,7 @@ #include "qemu-common.h" #include "hw/arm/arm.h" +#include "hw/intc/arm_gic.h" #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ @@ -26,12 +27,25 @@ #define XLNX_ZYNQMP_NUM_CPUS 4 +#define XLNX_ZYNQMP_GIC_REGIONS 2 + +/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets + * and under-decodes the 64k region. This mirrors the 4k regions to every 4k + * aligned address in the 64k region. To implement each GIC region needs a + * number of memory region aliases. + */ + +#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x4000 +#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1) + typedef struct XlnxZynqMPState { /*< private >*/ DeviceState parent_obj; /*< public >*/ ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS]; + GICState gic; + MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; } XlnxZynqMPState; #define XLNX_ZYNQMP_H -- cgit v1.2.3