From e8373c56531cec8eb48743f261e8b216bcda589a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 12 Oct 2020 11:58:00 +0200 Subject: hw/mips/cps: Expose input clock and connect it to CPU cores MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Expose a qdev input clock named 'clk-in', and connect it to each core to forward-propagate the clock. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-18-f4bug@amsat.org> --- hw/mips/cps.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'hw') diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 23c0f87e41..af7b58c4bd 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -22,6 +22,7 @@ #include "qemu/module.h" #include "hw/mips/cps.h" #include "hw/mips/mips.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "hw/mips/cpudevs.h" #include "sysemu/kvm.h" @@ -38,6 +39,7 @@ static void mips_cps_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); MIPSCPSState *s = MIPS_CPS(obj); + s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL); /* * Cover entire address space as there do not seem to be any * constraints for the base address of CPC and GIC. @@ -80,6 +82,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) errp)) { return; } + /* All cores use the same clock tree */ + qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) { return; -- cgit v1.2.3