From d4d230da08918183929c7d6cb54824b391536904 Mon Sep 17 00:00:00 2001
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Date: Wed, 5 Dec 2012 16:53:42 +1000
Subject: xilinx_axienet: Implement R_IS behaviour

The interrupt status register R_IS is the standard clear-on-write behaviour.
This was unimplemented and defaulting to updating the register to the written
value. Implemented clear-on-write.

Reported-by: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
 hw/xilinx_axienet.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'hw')

diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
index baae02bd66..f2e3bf1274 100644
--- a/hw/xilinx_axienet.c
+++ b/hw/xilinx_axienet.c
@@ -591,6 +591,10 @@ static void enet_write(void *opaque, hwaddr addr,
             s->maddr[s->fmi & 3][addr & 1] = value;
             break;
 
+        case R_IS:
+            s->regs[addr] &= ~value;
+            break;
+
         case 0x8000 ... 0x83ff:
             s->ext_mtable[addr - 0x8000] = value;
             break;
-- 
cgit v1.2.3