From 059ca2bf0d882349aa002e10e3769d25cb923eb4 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:37 +0000 Subject: char/cadence_uart: Mark struct fields as public/private As per current QOM conventions. Signed-off-by: Peter Crosthwaite Message-id: a1e31bd62e9709ffb9b3efc6c120f83f30b7a660.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index f18db53bca..a7b2f2148c 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -110,7 +110,9 @@ #define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART) typedef struct { + /*< private >*/ SysBusDevice parent_obj; + /*< public >*/ MemoryRegion iomem; uint32_t r[R_MAX]; -- cgit v1.2.3 From 589bfb6888385ae1767fe2f94528f2dacf59509a Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:37 +0000 Subject: char/cadence_uart: Add missing uart_update_state This should be rechecked on bus write accesses as such accesses may change the underlying state that generates the interrupt. Particular relevant for when the guest touches the interrupt status or mask. Signed-off-by: Peter Crosthwaite Message-id: 1c250cd61b7b8de492fbc8b79b8370958a56d83b.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index a7b2f2148c..fb9db89ee9 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -403,6 +403,7 @@ static void uart_write(void *opaque, hwaddr offset, uart_parameters_setup(s); break; } + uart_update_status(s); } static uint64_t uart_read(void *opaque, hwaddr offset, -- cgit v1.2.3 From 823dd48761a668c8e787cb9cf07234b656a05926 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:38 +0000 Subject: char/cadence_uart: Fix reset. Don't reset the uart as an init step. Register the reset function as a proper reset fn instead. Signed-off-by: Peter Crosthwaite Message-id: d82cd2e65e5a6f8b6deeecb6cced61f0bf3f8c89.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index fb9db89ee9..7edc1196f3 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -431,8 +431,10 @@ static const MemoryRegionOps uart_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void cadence_uart_reset(UartState *s) +static void cadence_uart_reset(DeviceState *dev) { + UartState *s = CADENCE_UART(dev); + s->r[R_CR] = 0x00000128; s->r[R_IMR] = 0; s->r[R_CISR] = 0; @@ -465,8 +467,6 @@ static int cadence_uart_init(SysBusDevice *dev) s->chr = qemu_char_get_next_serial(); - cadence_uart_reset(s); - if (s->chr) { qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive, uart_event, s); @@ -508,6 +508,7 @@ static void cadence_uart_class_init(ObjectClass *klass, void *data) sdc->init = cadence_uart_init; dc->vmsd = &vmstate_cadence_uart; + dc->reset = cadence_uart_reset; } static const TypeInfo cadence_uart_info = { -- cgit v1.2.3 From 1e77c91e2422ffa366fa5a0a39a6e7cc24a102ca Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:38 +0000 Subject: char/cadence_uart: s/r_fifo/rx_fifo Rename this field to match the many other uses of "rx". Xilinx docmentation (UG585) also refers to this as "RxFIFO". Signed-off-by: Peter Crosthwaite Message-id: 7386d7cee0ea175f7e53ed5ff045265528d34e32.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 7edc1196f3..d6abc5b985 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -116,7 +116,7 @@ typedef struct { MemoryRegion iomem; uint32_t r[R_MAX]; - uint8_t r_fifo[RX_FIFO_SIZE]; + uint8_t rx_fifo[RX_FIFO_SIZE]; uint32_t rx_wpos; uint32_t rx_count; uint64_t char_tx_time; @@ -280,7 +280,7 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) s->r[R_CISR] |= UART_INTR_ROVR; } else { for (i = 0; i < size; i++) { - s->r_fifo[s->rx_wpos] = buf[i]; + s->rx_fifo[s->rx_wpos] = buf[i]; s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE; s->rx_count++; @@ -344,7 +344,7 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c) if (s->rx_count) { uint32_t rx_rpos = (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE; - *c = s->r_fifo[rx_rpos]; + *c = s->rx_fifo[rx_rpos]; s->rx_count--; if (!s->rx_count) { @@ -492,7 +492,7 @@ static const VMStateDescription vmstate_cadence_uart = { .post_load = cadence_uart_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(r, UartState, R_MAX), - VMSTATE_UINT8_ARRAY(r_fifo, UartState, RX_FIFO_SIZE), + VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE), VMSTATE_UINT32(rx_count, UartState), VMSTATE_UINT32(rx_wpos, UartState), VMSTATE_TIMER(fifo_trigger_handle, UartState), -- cgit v1.2.3 From 676f4c095d53841626b1ee2cbc7a53b4f6239e4e Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:38 +0000 Subject: char/cadence_uart: Simplify status generation The status register bits are always pure functions of other device state. Move the generation of these bits to the update_status() function to simplify. Makes developing much easier as theres now no need to recheck status bits on all the changes to rx/tx fifo state. Signed-off-by: Peter Crosthwaite Message-id: 321994929f789096975104f99c55732774be4cae.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 33 ++++++++------------------------- 1 file changed, 8 insertions(+), 25 deletions(-) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index d6abc5b985..ddd7267259 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -128,6 +128,13 @@ typedef struct { static void uart_update_status(UartState *s) { + s->r[R_SR] = 0; + + s->r[R_SR] |= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0; + s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; + s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; + + s->r[R_SR] |= UART_SR_INTR_TEMPTY; s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); } @@ -166,15 +173,10 @@ static void uart_rx_reset(UartState *s) if (s->chr) { qemu_chr_accept_input(s->chr); } - - s->r[R_SR] |= UART_SR_INTR_REMPTY; - s->r[R_SR] &= ~UART_SR_INTR_RFUL; } static void uart_tx_reset(UartState *s) { - s->r[R_SR] |= UART_SR_INTR_TEMPTY; - s->r[R_SR] &= ~UART_SR_INTR_TFUL; } static void uart_send_breaks(UartState *s) @@ -274,8 +276,6 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) return; } - s->r[R_SR] &= ~UART_SR_INTR_REMPTY; - if (s->rx_count == RX_FIFO_SIZE) { s->r[R_CISR] |= UART_INTR_ROVR; } else { @@ -283,15 +283,6 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) s->rx_fifo[s->rx_wpos] = buf[i]; s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE; s->rx_count++; - - if (s->rx_count == RX_FIFO_SIZE) { - s->r[R_SR] |= UART_SR_INTR_RFUL; - break; - } - - if (s->rx_count >= s->r[R_RTRIG]) { - s->r[R_SR] |= UART_SR_INTR_RTRIG; - } } timer_mod(s->fifo_trigger_handle, new_rx_time + (s->char_tx_time * 4)); @@ -339,26 +330,17 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c) return; } - s->r[R_SR] &= ~UART_SR_INTR_RFUL; - if (s->rx_count) { uint32_t rx_rpos = (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE; *c = s->rx_fifo[rx_rpos]; s->rx_count--; - if (!s->rx_count) { - s->r[R_SR] |= UART_SR_INTR_REMPTY; - } qemu_chr_accept_input(s->chr); } else { *c = 0; - s->r[R_SR] |= UART_SR_INTR_REMPTY; } - if (s->rx_count < s->r[R_RTRIG]) { - s->r[R_SR] &= ~UART_SR_INTR_RTRIG; - } uart_update_status(s); } @@ -447,6 +429,7 @@ static void cadence_uart_reset(DeviceState *dev) s->rx_count = 0; s->rx_wpos = 0; + uart_update_status(s); } static int cadence_uart_init(SysBusDevice *dev) -- cgit v1.2.3 From 11a239a51ccbf27a22e2aa5f423ff1d6f5df65a7 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:39 +0000 Subject: char/cadence_uart: Define Missing SR/ISR fields Some (interrupt) status register bits relating to the TxFIFO path were not defined. Define them. This prepares support for proper Tx data path flow control. Signed-off-by: Peter Crosthwaite Message-id: 2068b963f0af8cc834c353944e9fa816d950b163.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index ddd7267259..216eed7442 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -34,6 +34,9 @@ #define UART_SR_INTR_RFUL 0x00000004 #define UART_SR_INTR_TEMPTY 0x00000008 #define UART_SR_INTR_TFUL 0x00000010 +/* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ +#define UART_SR_TTRIG 0x00002000 +#define UART_INTR_TTRIG 0x00000400 /* bits fields in CSR that correlate to CISR. If any of these bits are set in * SR, then the same bit in CISR is set high too */ #define UART_SR_TO_CISR_MASK 0x0000001F @@ -43,6 +46,7 @@ #define UART_INTR_PARE 0x00000080 #define UART_INTR_TIMEOUT 0x00000100 #define UART_INTR_DMSI 0x00000200 +#define UART_INTR_TOVR 0x00001000 #define UART_SR_RACTIVE 0x00000400 #define UART_SR_TACTIVE 0x00000800 -- cgit v1.2.3 From 2152e08ad12180f307bc5b838134ab745767d2e5 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:39 +0000 Subject: char/cadence_uart: Remove TX timer & add TX FIFO state This tx timer implementation is flawed. Despite the controller attempting to time the guest visable assertion of the TX-empty status bit (and corresponding interrupt) the controller is still transmitting characters instantaneously. There is also no sense of multiple character delay. The only side effect of this timer is assertion of tx-empty status. So just remove the timer completely and hold tx-empty as permanently asserted (its reset status). This matches the actual behaviour of instantaneous transmission. While we are VMSD version bumping, add the tx_fifo as device state to prepare for upcomming TxFIFO flow control. Implement the interrupt generation logic for the TxFIFO occupancy. Signed-off-by: Peter Crosthwaite Message-id: 7a208a7eb8d79d6429fe28b1396c3104371807b2.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 44 +++++++++++++------------------------------- 1 file changed, 13 insertions(+), 31 deletions(-) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 216eed7442..3eeadb18fd 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -121,13 +121,14 @@ typedef struct { MemoryRegion iomem; uint32_t r[R_MAX]; uint8_t rx_fifo[RX_FIFO_SIZE]; + uint8_t tx_fifo[TX_FIFO_SIZE]; uint32_t rx_wpos; uint32_t rx_count; + uint32_t tx_count; uint64_t char_tx_time; CharDriverState *chr; qemu_irq irq; QEMUTimer *fifo_trigger_handle; - QEMUTimer *tx_time_handle; } UartState; static void uart_update_status(UartState *s) @@ -138,8 +139,12 @@ static void uart_update_status(UartState *s) s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; - s->r[R_SR] |= UART_SR_INTR_TEMPTY; + s->r[R_SR] |= s->tx_count == TX_FIFO_SIZE ? UART_SR_INTR_TFUL : 0; + s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; + s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; + s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; + s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); } @@ -152,24 +157,6 @@ static void fifo_trigger_update(void *opaque) uart_update_status(s); } -static void uart_tx_redo(UartState *s) -{ - uint64_t new_tx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - - timer_mod(s->tx_time_handle, new_tx_time + s->char_tx_time); - - s->r[R_SR] |= UART_SR_INTR_TEMPTY; - - uart_update_status(s); -} - -static void uart_tx_write(void *opaque) -{ - UartState *s = (UartState *)opaque; - - uart_tx_redo(s); -} - static void uart_rx_reset(UartState *s) { s->rx_wpos = 0; @@ -181,6 +168,7 @@ static void uart_rx_reset(UartState *s) static void uart_tx_reset(UartState *s) { + s->tx_count = 0; } static void uart_send_breaks(UartState *s) @@ -261,10 +249,6 @@ static void uart_ctrl_update(UartState *s) s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); - if ((s->r[R_CR] & UART_CR_TX_EN) && !(s->r[R_CR] & UART_CR_TX_DIS)) { - uart_tx_redo(s); - } - if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { uart_send_breaks(s); } @@ -447,9 +431,6 @@ static int cadence_uart_init(SysBusDevice *dev) s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *)fifo_trigger_update, s); - s->tx_time_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, - (QEMUTimerCB *)uart_tx_write, s); - s->char_tx_time = (get_ticks_per_sec() / 9600) * 10; s->chr = qemu_char_get_next_serial(); @@ -473,17 +454,18 @@ static int cadence_uart_post_load(void *opaque, int version_id) static const VMStateDescription vmstate_cadence_uart = { .name = "cadence_uart", - .version_id = 1, - .minimum_version_id = 1, - .minimum_version_id_old = 1, + .version_id = 2, + .minimum_version_id = 2, + .minimum_version_id_old = 2, .post_load = cadence_uart_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(r, UartState, R_MAX), VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE), + VMSTATE_UINT8_ARRAY(tx_fifo, UartState, RX_FIFO_SIZE), VMSTATE_UINT32(rx_count, UartState), + VMSTATE_UINT32(tx_count, UartState), VMSTATE_UINT32(rx_wpos, UartState), VMSTATE_TIMER(fifo_trigger_handle, UartState), - VMSTATE_TIMER(tx_time_handle, UartState), VMSTATE_END_OF_LIST() } }; -- cgit v1.2.3 From d0ac820fe4152ea3a57fc3fa9f732cc9524017a4 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:39 +0000 Subject: char/cadence_uart: Fix can_receive logic The can_receive logic was only taking into account the RxFIFO occupancy. RxFIFO population is only used for the echo and normal modes however. Improve the logic to correctly return the true number of receivable characters based on the current mode: Normal mode: RxFIFO vacancy. Remote loopback: TxFIFO vacancy. Echo mode: The min of the TxFIFO and RxFIFO vacancies. Local Loopback: Return non-zero (to implement droppage) Signed-off-by: Peter Crosthwaite Message-id: 36a58440c9ca5080151e95765c2c81342de8a8df.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 3eeadb18fd..3bcaf2905d 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -233,8 +233,16 @@ static void uart_parameters_setup(UartState *s) static int uart_can_receive(void *opaque) { UartState *s = (UartState *)opaque; + int ret = MAX(RX_FIFO_SIZE, TX_FIFO_SIZE); + uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; - return RX_FIFO_SIZE - s->rx_count; + if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { + ret = MIN(ret, RX_FIFO_SIZE - s->rx_count); + } + if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { + ret = MIN(ret, TX_FIFO_SIZE - s->tx_count); + } + return ret; } static void uart_ctrl_update(UartState *s) -- cgit v1.2.3 From 86baecc3e43510c3bef03a0d7e947221823864d3 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:40 +0000 Subject: char/cadence_uart: Use the TX fifo for transmission Populate the TxFIFO with the Tx data before sending. Prepares support for proper Tx flow control implementation. Signed-off-by: Peter Crosthwaite Message-id: bdf7f8af2ef02839bea18665701bc2612f7baa6f.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 3bcaf2905d..be32126bdc 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -292,7 +292,22 @@ static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size) return; } - qemu_chr_fe_write_all(s->chr, buf, size); + if (size > TX_FIFO_SIZE - s->tx_count) { + size = TX_FIFO_SIZE - s->tx_count; + /* + * This can only be a guest error via a bad tx fifo register push, + * as can_receive() should stop remote loop and echo modes ever getting + * us to here. + */ + qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow"); + s->r[R_CISR] |= UART_INTR_ROVR; + } + + memcpy(s->tx_fifo + s->tx_count, buf, size); + s->tx_count += size; + + qemu_chr_fe_write_all(s->chr, s->tx_fifo, s->tx_count); + s->tx_count = 0; } static void uart_receive(void *opaque, const uint8_t *buf, int size) -- cgit v1.2.3 From 1e5d8cacb7fe509aa793ad844105fbc4fe02e015 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:40 +0000 Subject: char/cadence_uart: Delete redundant rx rst logic uart_rx_reset() called immediately above already does this. Remove. Signed-off-by: Peter Crosthwaite Message-id: 05e30826496cf2579084ed801ac0b2c0d0a3071f.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index be32126bdc..8a9ef81d2c 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -438,8 +438,6 @@ static void cadence_uart_reset(DeviceState *dev) uart_rx_reset(s); uart_tx_reset(s); - s->rx_count = 0; - s->rx_wpos = 0; uart_update_status(s); } -- cgit v1.2.3 From 38acd64b1cc8b9589e155d16ba4a0ccf9dc95ae4 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 6 Jan 2014 10:16:40 +0000 Subject: char/cadence_uart: Implement Tx flow control If the UART back-end blocks, buffer in the Tx FIFO to try again later. This stops the IO-thread busy waiting on char back-ends (which causes all sorts of performance problems). Signed-off-by: Peter Crosthwaite Message-id: 4bea048b3ab38425701d82ccc1ab92545c26b79c.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 8a9ef81d2c..1012f1ad64 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -286,6 +286,34 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) uart_update_status(s); } +static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, + void *opaque) +{ + UartState *s = opaque; + int ret; + + /* instant drain the fifo when there's no back-end */ + if (!s->chr) { + s->tx_count = 0; + } + + if (!s->tx_count) { + return FALSE; + } + + ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count); + s->tx_count -= ret; + memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); + + if (s->tx_count) { + int r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT, cadence_uart_xmit, s); + assert(r); + } + + uart_update_status(s); + return FALSE; +} + static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size) { if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { @@ -306,8 +334,7 @@ static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size) memcpy(s->tx_fifo + s->tx_count, buf, size); s->tx_count += size; - qemu_chr_fe_write_all(s->chr, s->tx_fifo, s->tx_count); - s->tx_count = 0; + cadence_uart_xmit(NULL, G_IO_OUT, s); } static void uart_receive(void *opaque, const uint8_t *buf, int size) -- cgit v1.2.3 From 7fcd57e80d134deb925aa47934040a39fd5fa1e0 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Fri, 3 Jan 2014 17:58:43 -0800 Subject: arm/xilinx_zynq: Always instantiate the GEMs Don't conditionalise GEM instantiation on networking attachments. The device should always be present even if not attached to a network. This allows for probing of the device by expectant guests (such as OS's). This is needed because sysbus (or AXI in Xilinx's real hw case) is not self identifying so the guest has no dynamic way of detecting device absence. Also allows for testing of the GEM in loopback mode with -net none. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Message-id: 55649779a68ee3ff54b24c339b6fdbdccd1f0ed7.1388800598.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) (limited to 'hw') diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 17251c7a65..98e0958a77 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -49,9 +49,11 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) DeviceState *dev; SysBusDevice *s; - qemu_check_nic_model(nd, "cadence_gem"); dev = qdev_create(NULL, "cadence_gem"); - qdev_set_nic_properties(dev, nd); + if (nd->used) { + qemu_check_nic_model(nd, "cadence_gem"); + qdev_set_nic_properties(dev, nd); + } qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_mmio_map(s, 0, base); @@ -113,7 +115,6 @@ static void zynq_init(QEMUMachineInitArgs *args) DeviceState *dev; SysBusDevice *busdev; qemu_irq pic[64]; - NICInfo *nd; Error *err = NULL; int n; @@ -190,14 +191,8 @@ static void zynq_init(QEMUMachineInitArgs *args) sysbus_create_varargs("cadence_ttc", 0xF8002000, pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); - for (n = 0; n < nb_nics; n++) { - nd = &nd_table[n]; - if (n == 0) { - gem_init(nd, 0xE000B000, pic[54-IRQ_OFFSET]); - } else if (n == 1) { - gem_init(nd, 0xE000C000, pic[77-IRQ_OFFSET]); - } - } + gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); + gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); dev = qdev_create(NULL, "generic-sdhci"); qdev_init_nofail(dev); -- cgit v1.2.3 From 04050c5c6aa6f9c086a63a30b182b996fb2d3d02 Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Fri, 20 Dec 2013 22:09:32 -0800 Subject: arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER TRIGGER can really mean mean anything (e.g. was it triggered, is it level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to make the code comprehensible without looking up the data structure. Reviewed-by: Peter Maydell Signed-off-by: Christoffer Dall Message-id: 1387606179-22709-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 12 ++++++------ hw/intc/arm_gic_common.c | 4 ++-- hw/intc/gic_internal.h | 6 +++--- 3 files changed, 11 insertions(+), 11 deletions(-) (limited to 'hw') diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d431b7a881..27c258a6fd 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -128,7 +128,7 @@ static void gic_set_irq(void *opaque, int irq, int level) if (level) { GIC_SET_LEVEL(irq, cm); - if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { + if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { DPRINTF("Set %d pending mask %x\n", irq, target); GIC_SET_PENDING(irq, target); } @@ -188,7 +188,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq) return; /* No active IRQ. */ /* Mark level triggered interrupts as pending if they are still raised. */ - if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) + if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { DPRINTF("Set %d pending mask %x\n", irq, cm); GIC_SET_PENDING(irq, cm); @@ -311,7 +311,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) for (i = 0; i < 4; i++) { if (GIC_TEST_MODEL(irq + i)) res |= (1 << (i * 2)); - if (GIC_TEST_TRIGGER(irq + i)) + if (GIC_TEST_EDGE_TRIGGER(irq + i)) res |= (2 << (i * 2)); } } else if (offset < 0xfe0) { @@ -386,7 +386,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, /* If a raised level triggered IRQ enabled then mark is as pending. */ if (GIC_TEST_LEVEL(irq + i, mask) - && !GIC_TEST_TRIGGER(irq + i)) { + && !GIC_TEST_EDGE_TRIGGER(irq + i)) { DPRINTF("Set %d pending mask %x\n", irq + i, mask); GIC_SET_PENDING(irq + i, mask); } @@ -478,9 +478,9 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, GIC_CLEAR_MODEL(irq + i); } if (value & (2 << (i * 2))) { - GIC_SET_TRIGGER(irq + i); + GIC_SET_EDGE_TRIGGER(irq + i); } else { - GIC_CLEAR_TRIGGER(irq + i); + GIC_CLEAR_EDGE_TRIGGER(irq + i); } } } else { diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index c7658508dd..710607b044 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -51,7 +51,7 @@ static const VMStateDescription vmstate_gic_irq_state = { VMSTATE_UINT8(active, gic_irq_state), VMSTATE_UINT8(level, gic_irq_state), VMSTATE_BOOL(model, gic_irq_state), - VMSTATE_BOOL(trigger, gic_irq_state), + VMSTATE_BOOL(edge_trigger, gic_irq_state), VMSTATE_END_OF_LIST() } }; @@ -126,7 +126,7 @@ static void arm_gic_common_reset(DeviceState *dev) } for (i = 0; i < 16; i++) { GIC_SET_ENABLED(i, ALL_CPU_MASK); - GIC_SET_TRIGGER(i); + GIC_SET_EDGE_TRIGGER(i); } if (s->num_cpu == 1) { /* For uniprocessor GICs all interrupts always target the sole CPU */ diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 3989fd1bd5..efac78d44b 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -44,9 +44,9 @@ #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm) #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm) #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) -#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = true -#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = false -#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger +#define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = true +#define GIC_CLEAR_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = false +#define GIC_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger) #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ s->priority1[irq][cpu] : \ s->priority2[(irq) - GIC_INTERNAL]) -- cgit v1.2.3 From 9df90ad078ec782d1339bd6879b6ea117f9759f7 Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Fri, 20 Dec 2013 22:09:33 -0800 Subject: hw: arm_gic: Introduce gic_set_priority function To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this function to set the priority of interrupts. Reviewed-by: Peter Maydell Signed-off-by: Christoffer Dall Message-id: 1387606179-22709-3-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 15 ++++++++++----- hw/intc/gic_internal.h | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) (limited to 'hw') diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 27c258a6fd..6c5965093e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -168,6 +168,15 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu) return new_irq; } +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val) +{ + if (irq < GIC_INTERNAL) { + s->priority1[irq][cpu] = val; + } else { + s->priority2[(irq) - GIC_INTERNAL] = val; + } +} + void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; @@ -443,11 +452,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x400) + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < GIC_INTERNAL) { - s->priority1[irq][cpu] = value; - } else { - s->priority2[irq - GIC_INTERNAL] = value; - } + gic_set_priority(s, cpu, irq, value); } else if (offset < 0xc00) { /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the * annoying exception of the 11MPCore's GIC. diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index efac78d44b..8c02d5888c 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -61,5 +61,6 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu); void gic_complete_irq(GICState *s, int cpu, int irq); void gic_update(GICState *s); void gic_init_irqs_and_distributor(GICState *s, int num_irq); +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); #endif /* !QEMU_ARM_GIC_INTERNAL_H */ -- cgit v1.2.3