From 137feaa9a1622620adf19c0b707883dd990738e2 Mon Sep 17 00:00:00 2001 From: Fabian Aggeler Date: Thu, 11 Dec 2014 12:07:50 +0000 Subject: target-arm: add SCTLR_EL3 and make SCTLR banked Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell Message-id: 1416242878-876-14-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell --- hw/arm/pxa2xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 693dfec9f2..11d51afcf9 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -273,7 +273,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, case 3: s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; - s->cpu->env.cp15.c1_sys = 0; + s->cpu->env.cp15.sctlr_ns = 0; s->cpu->env.cp15.c1_coproc = 0; s->cpu->env.cp15.ttbr0_el1 = 0; s->cpu->env.cp15.c3 = 0; -- cgit v1.2.3 From 7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc Mon Sep 17 00:00:00 2001 From: Fabian Aggeler Date: Thu, 11 Dec 2014 12:07:51 +0000 Subject: target-arm: make TTBR0/1 banked Adds secure and non-secure bank register suport for TTBR0 and TTBR1. Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as well as a CP register definition for TTBR0_EL3. Added a union containing both EL based array fields and secure and non-secure fields mapped to them. Updated accesses to use A32_BANKED_CURRENT_REG_GET macro. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell Message-id: 1416242878-876-17-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell --- hw/arm/pxa2xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 11d51afcf9..2b00b598ca 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -275,7 +275,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; s->cpu->env.cp15.sctlr_ns = 0; s->cpu->env.cp15.c1_coproc = 0; - s->cpu->env.cp15.ttbr0_el1 = 0; + s->cpu->env.cp15.ttbr0_el[1] = 0; s->cpu->env.cp15.c3 = 0; s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ -- cgit v1.2.3 From 0c17d68c1d3d6c35f37f5692042d2edb65c8bcc0 Mon Sep 17 00:00:00 2001 From: Fabian Aggeler Date: Thu, 11 Dec 2014 12:07:51 +0000 Subject: target-arm: make DACR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell Message-id: 1416242878-876-19-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell --- hw/arm/pxa2xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 2b00b598ca..8967cc4e0b 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -276,7 +276,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, s->cpu->env.cp15.sctlr_ns = 0; s->cpu->env.cp15.c1_coproc = 0; s->cpu->env.cp15.ttbr0_el[1] = 0; - s->cpu->env.cp15.c3 = 0; + s->cpu->env.cp15.dacr_ns = 0; s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ -- cgit v1.2.3 From b1ab03af890b2b6c5bafc9344b7fe05b392180a5 Mon Sep 17 00:00:00 2001 From: Nikita Belov Date: Thu, 11 Dec 2014 12:07:52 +0000 Subject: hw/arm/realview.c: Fix memory leak in realview_init() Variable 'ram_lo' is allocated unconditionally, but used only in some cases. When it is unused pointer will be lost at function exit, resulting in a memory leak. Allocate memory for 'ram_lo' only if it is needed. Valgrind output: ==16879== 240 bytes in 1 blocks are definitely lost in loss record 6,033 of 7,018 ==16879== at 0x4C2AB80: malloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so) ==16879== by 0x33D2CE: malloc_and_trace (vl.c:2804) ==16879== by 0x509E610: g_malloc (in /lib/x86_64-linux-gnu/libglib-2.0.so.0.4000.0) ==16879== by 0x288836: realview_init (realview.c:55) ==16879== by 0x28988C: realview_pb_a8_init (realview.c:375) ==16879== by 0x341426: main (vl.c:4413) Signed-off-by: Nikita Belov Reviewed-by: Markus Armbruster Signed-off-by: Peter Maydell --- hw/arm/realview.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/arm/realview.c b/hw/arm/realview.c index af65aa4082..d41ec97a23 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -52,7 +52,7 @@ static void realview_init(MachineState *machine, CPUARMState *env; ObjectClass *cpu_oc; MemoryRegion *sysmem = get_system_memory(); - MemoryRegion *ram_lo = g_new(MemoryRegion, 1); + MemoryRegion *ram_lo; MemoryRegion *ram_hi = g_new(MemoryRegion, 1); MemoryRegion *ram_alias = g_new(MemoryRegion, 1); MemoryRegion *ram_hack = g_new(MemoryRegion, 1); @@ -135,6 +135,7 @@ static void realview_init(MachineState *machine, if (is_pb && ram_size > 0x20000000) { /* Core tile RAM. */ + ram_lo = g_new(MemoryRegion, 1); low_ram_size = ram_size - 0x20000000; ram_size = 0x20000000; memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, -- cgit v1.2.3 From a554ecb49d0021fd8bb0fd4f2f6be807b3c8b54f Mon Sep 17 00:00:00 2001 From: zhanghailiang Date: Thu, 11 Dec 2014 12:07:53 +0000 Subject: hw/arm/boot: fix uninitialized scalar variable warning reported by coverity Coverity reports the 'size' may be used uninitialized, but that can't happen, because the caller has checked "if (binfo->dtb_filename || binfo->get_dtb)" before call 'load_dtb'. Here we simply remove the 'if (binfo->get_dtb)' to satisfy coverity. Signed-off-by: zhanghailiang Message-id: 1416826240-12368-1-git-send-email-zhang.zhanghailiang@huawei.com Signed-off-by: Peter Maydell --- hw/arm/boot.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 0014c34ddd..e6a3c5bcfb 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -329,6 +329,8 @@ static void set_kernel_args_old(const struct arm_boot_info *info) * Returns: the size of the device tree image on success, * 0 if the image size exceeds the limit, * -1 on errors. + * + * Note: Must not be called unless have_dtb(binfo) is true. */ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, hwaddr addr_limit) @@ -352,7 +354,7 @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, goto fail; } g_free(filename); - } else if (binfo->get_dtb) { + } else { fdt = binfo->get_dtb(binfo, &size); if (!fdt) { fprintf(stderr, "Board was unable to create a dtb blob\n"); -- cgit v1.2.3 From 72149414e25784de60b821fe67c56108a5b03ce1 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 11 Dec 2014 12:07:53 +0000 Subject: arm_gic_kvm: Tell kernel about number of IRQs Newer kernels support a device attribute on the GIC which allows us to tell it how many IRQs this GIC instance is configured with; use it, if it exists. Signed-off-by: Peter Maydell Reviewed-by: Christoffer Dall Message-id: 1417718679-1071-1-git-send-email-peter.maydell@linaro.org --- hw/intc/arm_gic_kvm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'hw') diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 5038885afd..1ad3eb0ff8 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -92,6 +92,21 @@ static bool kvm_arm_gic_can_save_restore(GICState *s) return s->dev_fd >= 0; } +static bool kvm_gic_supports_attr(GICState *s, int group, int attrnum) +{ + struct kvm_device_attr attr = { + .group = group, + .attr = attrnum, + .flags = 0, + }; + + if (s->dev_fd == -1) { + return false; + } + + return kvm_device_ioctl(s->dev_fd, KVM_HAS_DEVICE_ATTR, &attr) == 0; +} + static void kvm_gic_access(GICState *s, int group, int offset, int cpu, uint32_t *val, bool write) { @@ -553,6 +568,11 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) return; } + if (kvm_gic_supports_attr(s, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) { + uint32_t numirqs = s->num_irq; + kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, 0, &numirqs, 1); + } + /* Distributor */ memory_region_init_reservation(&s->iomem, OBJECT(s), "kvm-gic_dist", 0x1000); -- cgit v1.2.3