From 8d492c5f06e107b2f7ebeb66ccb25537cccbf269 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 4 Mar 2021 19:25:11 +0100 Subject: hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ISD MemoryRegion is implemented for 32-bit accesses. Simplify it by setting the MemoryRegionOps::impl min/max access size fields. Since the region is registered with a size of 0x1000 bytes, we can remove the hwaddr mask. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan Message-Id: <20210309142630.728014-3-f4bug@amsat.org> --- hw/mips/gt64xxx_pci.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'hw') diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 6eb73e7705..99b1690af1 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -385,13 +385,12 @@ static void gt64120_writel(void *opaque, hwaddr addr, { GT64120State *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); - uint32_t saddr; + uint32_t saddr = addr >> 2; if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); } - saddr = (addr & 0xfff) >> 2; switch (saddr) { /* CPU Configuration */ @@ -695,9 +694,8 @@ static uint64_t gt64120_readl(void *opaque, GT64120State *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t val; - uint32_t saddr; + uint32_t saddr = addr >> 2; - saddr = (addr & 0xfff) >> 2; switch (saddr) { /* CPU Configuration */ @@ -976,6 +974,10 @@ static const MemoryRegionOps isd_mem_ops = { .read = gt64120_readl, .write = gt64120_writel, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) -- cgit v1.2.3