From 8bf682a349258c3d4a4a4d4fa99ecf7045cf4608 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 2 Mar 2022 06:51:39 +0100 Subject: ppc/pnv: Add a OCC model for POWER10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Our OCC model is very mininal and POWER10 can simply reuse the OCC model we introduced for POWER9. Reviewed-by: David Gibson Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 10 ++++++++++ hw/ppc/pnv_occ.c | 16 ++++++++++++++++ 2 files changed, 26 insertions(+) (limited to 'hw') diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index f486fdfb5c..2431a7a5a3 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1582,6 +1582,7 @@ static void pnv_chip_power10_instance_init(Object *obj) "xive-fabric"); object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); + object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); } static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) @@ -1647,6 +1648,15 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) chip->fw_mr = &chip10->lpc.isa_fw; chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", (uint64_t) PNV10_LPCM_BASE(chip)); + + /* Create the simplified OCC model */ + object_property_set_link(OBJECT(&chip10->occ), "psi", OBJECT(&chip10->psi), + &error_abort); + if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, + &chip10->occ.xscom_regs); } static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 5a716c256e..4ed66f5e1f 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -236,7 +236,9 @@ static const MemoryRegionOps pnv_occ_power9_xscom_ops = { static void pnv_occ_power9_class_init(ObjectClass *klass, void *data) { PnvOCCClass *poc = PNV_OCC_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + dc->desc = "PowerNV OCC Controller (POWER9)"; poc->xscom_size = PNV9_XSCOM_OCC_SIZE; poc->xscom_ops = &pnv_occ_power9_xscom_ops; poc->psi_irq = PSIHB9_IRQ_OCC; @@ -249,6 +251,19 @@ static const TypeInfo pnv_occ_power9_type_info = { .class_init = pnv_occ_power9_class_init, }; +static void pnv_occ_power10_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "PowerNV OCC Controller (POWER10)"; +} + +static const TypeInfo pnv_occ_power10_type_info = { + .name = TYPE_PNV10_OCC, + .parent = TYPE_PNV9_OCC, + .class_init = pnv_occ_power10_class_init, +}; + static void pnv_occ_realize(DeviceState *dev, Error **errp) { PnvOCC *occ = PNV_OCC(dev); @@ -297,6 +312,7 @@ static void pnv_occ_register_types(void) type_register_static(&pnv_occ_type_info); type_register_static(&pnv_occ_power8_type_info); type_register_static(&pnv_occ_power9_type_info); + type_register_static(&pnv_occ_power10_type_info); } type_init(pnv_occ_register_types); -- cgit v1.2.3