From fa92bd4af71bed76bf57bb1c8b5465414a52ab3f Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 23 Jan 2019 19:26:52 -0800 Subject: target/xtensa: fix access to the INTERRUPT SR INTERRUPT special register may be changed both by the core (by writing to INTSET and INTCLEAR registers) and by external events (by triggering and clearing HW IRQs). In MTTCG this state must be protected from concurrent access, otherwise interrupts may be lost or spurious interrupts may be detected. Use atomic operations to change INTSET SR. Fix wsr.intset so that it soesn't clear any bits. Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI. Signed-off-by: Max Filippov --- hw/xtensa/pic_cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw/xtensa') diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c index 0e812d7f06..7e4c65e5ec 100644 --- a/hw/xtensa/pic_cpu.c +++ b/hw/xtensa/pic_cpu.c @@ -68,9 +68,9 @@ static void xtensa_set_irq(void *opaque, int irq, int active) uint32_t irq_bit = 1 << irq; if (active) { - env->sregs[INTSET] |= irq_bit; + atomic_or(&env->sregs[INTSET], irq_bit); } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) { - env->sregs[INTSET] &= ~irq_bit; + atomic_and(&env->sregs[INTSET], ~irq_bit); } check_interrupts(env); -- cgit v1.2.3