From d3d6def468ff18b387ced3de79c0339aa7c1c78d Mon Sep 17 00:00:00 2001
From: Jamin Lin <jamin_lin@aspeedtech.com>
Date: Tue, 29 Oct 2024 17:17:24 +0800
Subject: hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600
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According to the datasheet of AST2600 description, interrupt status set by HW
and clear to "0" by software writing "1" on the specific bit.
Therefore, if firmware set the specific bit "1" in the interrupt status
register(0x34), the specific bit of "s->irq_sts" should be cleared 0.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Fixes: fadefada4d07 ("aspeed/timer: Add support for IRQ status register on the AST2600")
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/timer/aspeed_timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'hw/timer/aspeed_timer.c')
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 5af268ea9e..149f7cc5a6 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -580,7 +580,7 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
switch (offset) {
case 0x34:
- s->irq_sts &= tv;
+ s->irq_sts &= ~tv;
break;
case 0x3C:
aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
--
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