From 669b4983018cf13e2adafe1b1b4e1e4053eeb90b Mon Sep 17 00:00:00 2001 From: "Peter A. G. Crosthwaite" Date: Fri, 10 Aug 2012 13:16:11 +1000 Subject: xilinx_axi*: Re-implemented interconnect Re-implemented the interconnect between the Xilinx AXI ethernet and DMA controllers. A QOM interface "stream" is created, for the two stream interfaces. As per Edgars request, this is designed to be more generic than AXI-stream, so in the future we may see more clients of this interface beyond AXI stream. This is based primarily on Paolos original refactoring of the interconnect. Signed-off-by: Paolo Bonzini Signed-off-by: Peter A.G. Crosthwaite Signed-off-by: Edgar E. Iglesias --- hw/stream.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 hw/stream.h (limited to 'hw/stream.h') diff --git a/hw/stream.h b/hw/stream.h new file mode 100644 index 0000000000..21123a9089 --- /dev/null +++ b/hw/stream.h @@ -0,0 +1,31 @@ +#ifndef STREAM_H +#define STREAM_H 1 + +#include "qemu-common.h" +#include "qemu/object.h" + +/* stream slave. Used until qdev provides a generic way. */ +#define TYPE_STREAM_SLAVE "stream-slave" + +#define STREAM_SLAVE_CLASS(klass) \ + OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE) +#define STREAM_SLAVE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE) +#define STREAM_SLAVE(obj) \ + INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE) + +typedef struct StreamSlave { + Object Parent; +} StreamSlave; + +typedef struct StreamSlaveClass { + InterfaceClass parent; + + void (*push)(StreamSlave *obj, unsigned char *buf, size_t len, + uint32_t *app); +} StreamSlaveClass; + +void +stream_push(StreamSlave *sink, uint8_t *buf, size_t len, uint32_t *app); + +#endif /* STREAM_H */ -- cgit v1.2.3