From a9ec1c76d57491602b4d3b521f898905825ca848 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 17 Mar 2019 01:03:11 -0700 Subject: riscv: sifive_u: Correct UART0's IRQ in the device tree The UART0's interrupt vector is wrongly set to 1 in the device tree. Use SIFIVE_U_UART0_IRQ instead. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/riscv/sifive_u.c') diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 3199238ba0..5ecc47cea3 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -244,7 +244,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_CLOCK_FREQ / 2); qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); -- cgit v1.2.3