From 73f6ed97acdbf7aec72d368fd5e16c00e04ac172 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 1 Sep 2020 09:38:58 +0800 Subject: target/riscv: cpu: Set reset vector based on the configured property value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/riscv/sifive_e.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/riscv/sifive_e.c') diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index ca55cc438a..cd7560d8ec 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -177,6 +177,7 @@ static void sifive_e_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, TYPE_SIFIVE_GPIO); } -- cgit v1.2.3