From 75a6ed875ff0a2eb6b2971ae2098ed09963d7329 Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Tue, 9 Jun 2020 14:23:34 +0200 Subject: riscv: Fix to put "riscv.hart_array" devices on sysbus riscv_sifive_e_soc_init(), riscv_sifive_u_soc_init(), spike_board_init(), spike_v1_10_0_board_init(), spike_v1_09_1_board_init(), and riscv_virt_board_init() create "riscv-hart_array" sysbus devices in a way that leaves them unplugged. Create them the common way that puts them into the main system bus. Affects machines sifive_e, sifive_u, spike, spike_v1.10, spike_v1.9.1, and virt. Visible in "info qtree", here's the change for sifive_e: bus: main-system-bus type System + dev: riscv.hart_array, id "" + num-harts = 1 (0x1) + hartid-base = 0 (0x0) + cpu-type = "sifive-e31-riscv-cpu" dev: sifive_soc.gpio, id "" Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster Reviewed-by: Alistair Francis Message-Id: <20200609122339.937862-20-armbru@redhat.com> --- hw/riscv/opentitan.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'hw/riscv/opentitan.c') diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index b4fb836466..29887fe363 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -94,9 +94,8 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj) { LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); - object_initialize_child(obj, "cpus", &s->cpus, - sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, - &error_abort, NULL); + sysbus_init_child_obj(obj, "cpus", &s->cpus, + sizeof(s->cpus), TYPE_RISCV_HART_ARRAY); } static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) -- cgit v1.2.3