From db23e5d981ab22da0bfe1150f4828d08484b1fba Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 19 Oct 2021 20:16:58 -0700 Subject: target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20211020031709.359469-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- hw/riscv/boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/riscv/boot.c') diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 993bf89064..d1ffc7b56c 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -35,7 +35,7 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { - return riscv_cpu_is_32bit(&harts->harts[0].env); + return harts->harts[0].env.misa_mxl_max == MXL_RV32; } target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, -- cgit v1.2.3