From 933f73f13e5ceb9357e9c9d51ce39c43aa1d534f Mon Sep 17 00:00:00 2001
From: Bin Meng <bin.meng@windriver.com>
Date: Wed, 28 Oct 2020 13:30:03 +0800
Subject: hw/riscv: microchip_pfsoc: Connect DDR memory controller modules

Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'hw/riscv/Kconfig')

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 2df978fe8d..c8e50bde99 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -4,6 +4,7 @@ config IBEX
 config MICROCHIP_PFSOC
     bool
     select CADENCE_SDHCI
+    select MCHP_PFSOC_DMC
     select MCHP_PFSOC_MMUART
     select MSI_NONBROKEN
     select SIFIVE_CLINT
-- 
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