From cb3778a0455a2e5a48d7ef0ec8dc656313820389 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 12 Nov 2014 22:44:52 +0100 Subject: PPC: e500 pci host: Add support for ATMUs The e500 PCI controller has configurable windows that allow a guest OS to selectively map parts of the PCI bus space to CPU address space and to selectively map parts of the CPU address space for DMA requests into PCI visible address ranges. So far, we've simply assumed that this mapping is 1:1 and ignored it. However, the PCICSRBAR (CCSR mapped in PCI bus space) always has to live inside the first 32bits of address space. This means if we always treat all mappings as 1:1, this map will collide with our RAM map from the CPU's point of view. So this patch adds proper ATMU support which allows us to keep the PCICSRBAR below 32bits local to the PCI bus and have another, different window to PCI BARs at the upper end of address space. We leverage this on e500plat though, mpc8544ds stays virtually 1:1 like it was before, but now also goes via ATMU. With this patch, I can run guests with lots of RAM and not coincidently access MSI-X mappings while I really want to access RAM. Signed-off-by: Alexander Graf --- hw/ppc/e500.c | 6 ++---- hw/ppc/e500.h | 2 ++ hw/ppc/e500plat.c | 2 ++ hw/ppc/mpc8544ds.c | 2 ++ 4 files changed, 8 insertions(+), 4 deletions(-) (limited to 'hw/ppc') diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 1aaa5154d1..a2e60b4896 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -288,8 +288,8 @@ static int ppce500_load_device_tree(MachineState *machine, int len; uint32_t pci_ranges[14] = { - 0x2000000, 0x0, 0xc0000000, - 0x0, 0xc0000000, + 0x2000000, 0x0, params->pci_mmio_bus_base, + params->pci_mmio_base >> 32, params->pci_mmio_base, 0x0, 0x20000000, 0x1000000, 0x0, 0x0, @@ -915,8 +915,6 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) if (!pci_bus) printf("couldn't create PCI controller!\n"); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, params->pci_pio_base); - if (pci_bus) { /* Register network interfaces. */ for (i = 0; i < nb_nics; i++) { diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index d96f72d484..ef224ea5e6 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -19,6 +19,8 @@ typedef struct PPCE500Params { int platform_bus_num_irqs; hwaddr ccsrbar_base; hwaddr pci_pio_base; + hwaddr pci_mmio_base; + hwaddr pci_mmio_bus_base; hwaddr spin_base; } PPCE500Params; diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index 1b8a68d223..14b14eaa7d 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -43,6 +43,8 @@ static void e500plat_init(MachineState *machine) .platform_bus_num_irqs = 10, .ccsrbar_base = 0xFE0000000ULL, .pci_pio_base = 0xFE1000000ULL, + .pci_mmio_base = 0xC00000000ULL, + .pci_mmio_bus_base = 0xE0000000ULL, .spin_base = 0xFEF000000ULL, }; diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index fb74b3ff80..3a3b141e43 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -35,6 +35,8 @@ static void mpc8544ds_init(MachineState *machine) .fixup_devtree = mpc8544ds_fixup_devtree, .mpic_version = OPENPIC_MODEL_FSL_MPIC_20, .ccsrbar_base = 0xE0000000ULL, + .pci_mmio_base = 0xC0000000ULL, + .pci_mmio_bus_base = 0xC0000000ULL, .pci_pio_base = 0xE1000000ULL, .spin_base = 0xEF000000ULL, }; -- cgit v1.2.3