From 7ccc89b5c8015b3f0d6220601a1e5e3010d8c2e1 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Mon, 19 Feb 2018 11:34:25 +0100 Subject: ppc440: Add emulation of plb-pcix controller found in some 440 SoCs This is the PCIX controller found in newer 440 core SoCs e.g. the AMMC 460EX. The device tree refers to this as plb-pcix compared to the plb-pci controller in older 440 SoCs. Signed-off-by: BALATON Zoltan [dwg: Remove hwaddr from trace-events, that doesn't work with some trace backends] Signed-off-by: David Gibson --- hw/ppc/trace-events | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'hw/ppc/trace-events') diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index b7c3e64b5e..66ec7eda6e 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -99,3 +99,11 @@ mac99_uninorth_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"P # hw/ppc/ppc4xx_pci.c ppc4xx_pci_map_irq(int32_t devfn, int irq_num, int slot) "devfn 0x%x irq %d -> %d" ppc4xx_pci_set_irq(int irq_num) "PCI irq %d" + +# hw/ppc/ppc440_pcix.c +ppc440_pcix_map_irq(int32_t devfn, int irq_num, int slot) "devfn 0x%x irq %d -> %d" +ppc440_pcix_set_irq(int irq_num) "PCI irq %d" +ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of size=0x%" PRIx64 " to CPU=0x%" PRIx64 +ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64 +ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 +ppc440_pcix_reg_write(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64 -- cgit v1.2.3