From 734c44ea13272c3b3d5cd9345cc4df7ce9bd30b3 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sat, 24 Sep 2022 14:27:53 +0200 Subject: ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead of the separate arrays and adjust ppc4xx_sdram_init() and ppc440_sdram_init() accordingly as well as machines using these. Signed-off-by: BALATON Zoltan Reviewed-by: Cédric Le Goater Message-Id: Signed-off-by: Daniel Henrique Barboza --- hw/ppc/ppc405_uc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'hw/ppc/ppc405_uc.c') diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 1e02347e57..bcbf35bc14 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1074,14 +1074,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp) /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ - s->ram_bases[0] = 0; - s->ram_sizes[0] = s->ram_size; - memory_region_init_alias(&s->ram_banks[0], OBJECT(s), + s->ram_banks[0].base = 0; + s->ram_banks[0].size = s->ram_size; + memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s), "ppc405.sdram0", s->dram_mr, - s->ram_bases[0], s->ram_sizes[0]); + s->ram_banks[0].base, s->ram_banks[0].size); ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1, - s->ram_banks, s->ram_bases, s->ram_sizes); + s->ram_banks); /* External bus controller */ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { -- cgit v1.2.3