From 5d62725b2fefd59abf7225d620f7092fd34b8e11 Mon Sep 17 00:00:00 2001 From: Suraj Jitindar Singh Date: Thu, 28 Nov 2019 14:46:54 +0100 Subject: target/ppc: Implement the VTB for HV access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The virtual timebase register (VTB) is a 64-bit register which increments at the same rate as the timebase register, present on POWER8 and later processors. The register is able to be read/written by the hypervisor and read by the supervisor. All other accesses are illegal. Currently the VTB is just an alias for the timebase (TB) register. Implement the VTB so that is can be read/written independent of the TB. Make use of the existing method for accessing timebase facilities where by the compensation is stored and used to compute the value on reads/is updated on writes. Signed-off-by: Suraj Jitindar Singh [ clg: rebased on current ppc tree ] Signed-off-by: Cédric Le Goater Message-Id: <20191128134700.16091-2-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/ppc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'hw/ppc/ppc.c') diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 45834f98d1..d8c402811f 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -682,6 +682,22 @@ void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) &tb_env->atb_offset, ((uint64_t)value << 32) | tb); } +uint64_t cpu_ppc_load_vtb(CPUPPCState *env) +{ + ppc_tb_t *tb_env = env->tb_env; + + return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + tb_env->vtb_offset); +} + +void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value) +{ + ppc_tb_t *tb_env = env->tb_env; + + cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + &tb_env->vtb_offset, value); +} + static void cpu_ppc_tb_stop (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; -- cgit v1.2.3