From 4594f93a732f1f5936c3a5225481586e24bffa9e Mon Sep 17 00:00:00 2001 From: Fam Zheng Date: Wed, 15 Jul 2015 18:19:12 +0800 Subject: dp8393x: Flush packets when link comes up .can_receive callback changes semantics that once return 0, backend will try sending again until explicitly flushed, change the device to meet that. dp8393x_can_receive checks SONIC_CR_RXEN bit in SONIC_CR register and SONIC_ISR_RBE bit in SONIC_ISR register, try flushing the queue when either bit is being updated. Signed-off-by: Fam Zheng Reviewed-by: Stefan Hajnoczi Reviewed-by: Jason Wang Message-id: 1436955553-22791-12-git-send-email-famz@redhat.com Signed-off-by: Stefan Hajnoczi --- hw/net/dp8393x.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'hw/net') diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index cd889bce86..451ff72e50 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -327,9 +327,14 @@ static void dp8393x_do_stop_timer(dp8393xState *s) dp8393x_update_wt_regs(s); } +static int dp8393x_can_receive(NetClientState *nc); + static void dp8393x_do_receiver_enable(dp8393xState *s) { s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; + if (dp8393x_can_receive(s->nic->ncs)) { + qemu_flush_queued_packets(qemu_get_queue(s->nic)); + } } static void dp8393x_do_receiver_disable(dp8393xState *s) @@ -569,6 +574,9 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, dp8393x_do_read_rra(s); } dp8393x_update_irq(s); + if (dp8393x_can_receive(s->nic->ncs)) { + qemu_flush_queued_packets(qemu_get_queue(s->nic)); + } break; /* Ignore least significant bit */ case SONIC_RSA: -- cgit v1.2.3