From a8f07376c9b3e5bce736bdcf6f49dc63fa4a516b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 4 Sep 2019 09:05:06 +0200 Subject: aspeed/scu: Introduce a aspeed_scu_get_apb_freq() routine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The APB frequency can be calculated directly when needed from the HPLL_PARAM and CLK_SEL register values. This removes useless state in the model. Signed-off-by: Cédric Le Goater Message-id: 20190904070506.1052-11-clg@kaod.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/aspeed_scu.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) (limited to 'hw/misc') diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index d284458b9b..620b25c204 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -164,11 +164,12 @@ static uint32_t aspeed_scu_get_random(void) return num; } -static void aspeed_scu_set_apb_freq(AspeedSCUState *s) +uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s) { AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); + uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]); - s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) + return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) / asc->apb_divider; } @@ -228,7 +229,6 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, return; case CLK_SEL: s->regs[reg] = data; - aspeed_scu_set_apb_freq(s); break; case HW_STRAP1: if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { @@ -290,11 +290,11 @@ static const uint32_t hpll_ast2400_freqs[][4] = { { 400, 375, 350, 425 }, /* 25MHz */ }; -static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s) +static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) { - uint32_t hpll_reg = s->regs[HPLL_PARAM]; uint8_t freq_select; bool clk_25m_in; + uint32_t clkin = aspeed_scu_get_clkin(s); if (hpll_reg & SCU_AST2400_H_PLL_OFF) { return 0; @@ -311,7 +311,7 @@ static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s) multiplier = (2 - od) * ((n + 2) / (d + 1)); } - return s->clkin * multiplier; + return clkin * multiplier; } /* HW strapping */ @@ -321,10 +321,10 @@ static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s) return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000; } -static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s) +static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) { - uint32_t hpll_reg = s->regs[HPLL_PARAM]; uint32_t multiplier = 1; + uint32_t clkin = aspeed_scu_get_clkin(s); if (hpll_reg & SCU_H_PLL_OFF) { return 0; @@ -338,7 +338,7 @@ static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s) multiplier = ((m + 1) / (n + 1)) / (p + 1); } - return s->clkin * multiplier; + return clkin * multiplier; } static void aspeed_scu_reset(DeviceState *dev) @@ -351,13 +351,6 @@ static void aspeed_scu_reset(DeviceState *dev) s->regs[HW_STRAP1] = s->hw_strap1; s->regs[HW_STRAP2] = s->hw_strap2; s->regs[PROT_KEY] = s->hw_prot_key; - - /* - * All registers are set. Now compute the frequencies of the main clocks - */ - s->clkin = aspeed_scu_get_clkin(s); - s->hpll = asc->calc_hpll(s); - aspeed_scu_set_apb_freq(s); } static uint32_t aspeed_silicon_revs[] = { -- cgit v1.2.3