From 1c8a2388aa20029dc75f95c072fb98880e447ffe Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Mon, 27 Jun 2016 15:37:33 +0100 Subject: hw/misc: Add a model for the ASPEED System Control Unit The SCU is a collection of chip-level control registers that manage the various functions supported by ASPEED SoCs. Typically the bits control interactions with clocks, external hardware or reset behaviour, and we can largly take a hands-off approach to reads and writes. Firmware makes heavy use of the state to determine how to boot, but the reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev property is exposed so that the integrating SoC model can configure the silicon revision, which in-turn selects the appropriate reset values. Further qdev properties are exposed so the board model can configure the board-dependent hardware strapping. Almost all provided AST2400 reset values are specified by the datasheet. The notable exception is SOC_SCRATCH1, where we mark the DRAM as successfully initialised to avoid unnecessary dark corners in the SoC's u-boot support. Signed-off-by: Andrew Jeffery Message-id: 1466744305-23163-2-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell [PMM: drop unnecessary inttypes.h include] Signed-off-by: Peter Maydell --- hw/misc/trace-events | 3 +++ 1 file changed, 3 insertions(+) (limited to 'hw/misc/trace-events') diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 16b6701cbf..ea52a14d78 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -50,3 +50,6 @@ milkymist_pfpu_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" milkymist_pfpu_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" milkymist_pfpu_vectout(uint32_t a, uint32_t b, uint32_t dma_ptr) "a %08x b %08x dma_ptr %08x" milkymist_pfpu_pulse_irq(void) "Pulse IRQ" + +# hw/misc/aspeed_scu.c +aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 -- cgit v1.2.3