From 119df56bf059431190ed5509f6e3e459d7892723 Mon Sep 17 00:00:00 2001 From: Troy Lee Date: Tue, 11 Jan 2022 16:45:45 +0800 Subject: hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Aspeed 2600 SDK enables I3C support by default. The I3C driver will try to reset the device controller and set it up through device address table register. This dummy model responds to these registers with default values as listed in the ast2600v10 datasheet chapter 54.2. This avoids a guest machine kernel panic due to referencing an invalid kernel address if the device address table register isn't set correctly. Signed-off-by: Troy Lee Reviewed-by: Graeme Gregory Reviewed-by: Cédric Le Goater Tested-by: Graeme Gregory Message-id: 20220111084546.4145785-2-troy_lee@aspeedtech.com [PMM: tidied commit message; fixed format strings] Signed-off-by: Peter Maydell --- hw/misc/meson.build | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/misc/meson.build') diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 3f41a3a5b2..d1a1169108 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -105,6 +105,7 @@ softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c')) softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_hace.c', + 'aspeed_i3c.c', 'aspeed_lpc.c', 'aspeed_scu.c', 'aspeed_sdmc.c', -- cgit v1.2.3