From 14c179541bbf083f4b215ddb389828ad8b9d0b28 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 1 Sep 2020 14:21:51 +0200 Subject: aspeed/sdmc: Perform memory training MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows qemu to run the "normal" power on reset boot path through u-boot, where the DDR is trained. An enhancement would be to have the SCU bit stick across qemu reboots, but be unset on initial boot. Proper modelling would be to discard all writes to the phy setting regs at offset 0x100 - 0x400 and to model the phy status regs at offset 0x400. The status regs model would only need to account for offets 0x00, 0x50, 0x68 and 0x7c. Signed-off-by: Joel Stanley [ clg: checkpatch fixes ] Message-Id: <20200819100956.2216690-17-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/misc/aspeed_scu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/misc/aspeed_scu.c') diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 764222404b..dc6dd87c22 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -656,7 +656,7 @@ static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = { [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, - [AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */ + [AST2600_SDRAM_HANDSHAKE] = 0x00000000, [AST2600_HPLL_PARAM] = 0x1000405F, [AST2600_CHIP_ID0] = 0x1234ABCD, [AST2600_CHIP_ID1] = 0x88884444, -- cgit v1.2.3