From 6027d2740524cf04ab38564c0c299fddbeaa6723 Mon Sep 17 00:00:00 2001 From: Tianrui Zhao Date: Tue, 13 Dec 2022 20:50:16 +0800 Subject: hw/intc/loongarch_pch_msi: add irq number property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds irq number property for loongarch msi interrupt controller, and remove hard coding irq number macro. Signed-off-by: Tianrui Zhao Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20230104020518.2564263-2-zhaotianrui@loongson.cn> Signed-off-by: Song Gao --- hw/loongarch/virt.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'hw/loongarch') diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index c8a495ea30..82b2fb6a10 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -553,7 +553,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams) LoongArchCPU *lacpu; CPULoongArchState *env; CPUState *cpu_state; - int cpu, pin, i; + int cpu, pin, i, start, num; ipi = qdev_new(TYPE_LOONGARCH_IPI); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); @@ -633,14 +633,17 @@ static void loongarch_irq_init(LoongArchMachineState *lams) } pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); - qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START); + start = PCH_PIC_IRQ_NUM; + num = EXTIOI_IRQS - start; + qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); + qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); d = SYS_BUS_DEVICE(pch_msi); sysbus_realize_and_unref(d, &error_fatal); sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); - for (i = 0; i < PCH_MSI_IRQ_NUM; i++) { - /* Connect 192 pch_msi irqs to extioi */ + for (i = 0; i < num; i++) { + /* Connect pch_msi irqs to extioi */ qdev_connect_gpio_out(DEVICE(d), i, - qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START)); + qdev_get_gpio_in(extioi, i + start)); } loongarch_devices_init(pch_pic, lams); -- cgit v1.2.3